User`s manual

HS[1:0]

These bits select the High-Speed DAC Modes as follows (Table 6-11):

Table 6-11. High-Speed DAC Modes Select Codes

Simultaneous DAC0/111

DAC101

DAC0

Disabled00

DAC ModeHS0HS1

DACnR[1:0]

These bits select the independent gains/ranges for either DAC0 or DAC1. n=0 for DAC0

and n=1 for DAC1 (Table 6-12).

Table 6-12. Gains/Ranges for DAC0 or DAC1

153uVUnipolar 10V11

76uVUnipolar 5V01

305uVBipolar 10V10

153uVBipolar 5V00

LSB SizeRangeDACnR0DACnR1

READ

LDAEM

---------------

0123456789101112131415

LDAEM

This is the latched version of the DAC FIFO_EMPTY signal. This bit must be

write-write cleared with the

DAEMCL

bit.

1 = DAC FIFO was emptied at some point during FIFO'd operations. Incorrect data may

have been clocked into the selected DAC(s).

0 = DAC FIFO did not empty during FIFO'd operations. Status OK.

6.3 BADR2

The I/O Region defined by BADR2 contains the ADC Data register and the ADC FIFO clear

6.3.1 ADC Data Register

BADR2 + 0 ADC Data register.

WRITE

Writing to this register is only valid for SW initiated conversions. The ADC Pacer source must be set to

00 via the ADPS[1:0] bits. A null write to BADR2 + 0 with begin a single conversion.

Conversion status can be determined in two ways. The

EOC

bit in BADR1 + 0 can be polled until true

ADNEI

(the AD FIFO not-empty interrupt) can be used to signal that the ADC conversion is complete

and the data word is present in the FIFO.

READ