User`s manual

CALEN

This bit is used to enable Cal Mode.

1 = Selected Cal Source,

CSRC[2:0]

, is fed into Analog Channel 0.

0 = Analog Channel 0 functions as normal input.

SDI

Serial Data In. This bit is used to set serial address/data stream for the DAC8800

TrimDac and 8402 digital potentiometer. Used in conjunction with

SEL8800

and

SEL8402

bits.

6.2.5 DAC Control/Status Register

BADR1 + 8

This register selects the DAC gain/range, Pacer source, trigger and High-Speed Modes. In addition,

DAC FIFO status information is available. This is a Read/Write register.

WRITE

LDAEMCL

DACENSTARTDAPS0DAPS1HS0HS1-DAC0R0DAC0R1DAC1R0DAC1R1----

0123456789101112131415

LDAEMCL

This is a Write-clear bit to reset the latched EMPTY status flag of the DAC FIFO.

1 = Reset Empty Flag

0 = No Effect.

DACEN

This bit enables the Analog Out features of the board.

1 = DAC0/1 enabled.

0 = DAC0/1 disabled.

START

This bit starts FIFO'd DAC operations. If used with

DAXTRG

, the external trigger

signal, the

START

bit is used to arm the operation.

1 = Start/Arm FIFO operations.

0 = Disable FIFO'd DAC operations.

DAPS[1:0]

These bits select the DAC Pacer Source (Table 6-10):

Table 6-10. DAC Pacer Source Codes

External Rising Edge11

External Falling Edge01

Internal 82C54 Programmed via BADR3 + 9, + A

SW Convert00

Pacer SourceDAPS0DAPS1