User`s manual

Table 6-6. FIFO'd ADC Operations
Via SW after
INDX_GT=1
# Post-Trigger Samples < 1/2 FIFO
Pre-Trigger Mode
Via SW after XTRIG has
been detected
(INDX_GT=1)
11
ADHF
# Post-Trigger Samples > one FIFO
Pre-Trigger Mode
----------------------------------
1/2 FIFO < # Post-Trigger Samples < one FIFO
Pre-Trigger Mode
Via SW when remaining
count < one FIFO
------------------------
Via SW after XTRIG has
been detected
(INDX_GT=1)
01
ADC Pacer
# Samples <1/2 FIFO
Normal Mode
Via SW immediately
10
ADHF
# Samples >1 FIFO
Normal Mode
----------------------------------
1/2 FIFO < # Samples < one FIFO
Normal Mode
Via SW when remaining
count < one FIFO
------------------------
Via SW immediately
00
Sample CTR
Starts on...
FIFO ModeARM
is set...
FFM0PRTRG
C0SRC
This bit allows the user to select the clock source for user Counter 0.
1 = Internal 10 MHz oscillator
0 = External clock source input via CTR0CLK pin on 100-pin connector.
READ
-------XTRIG----INDX-GT---
0123456789101112131415
XTRIG
1 = External Trigger flip-flop has been set. This bit is write-cleared.
0 = External Trigger flip-flop reset. No trigger has been received.
INDX-GT
1 = PreTrigger index counter has completed its count
0 = PreTrigger index counter is not yet gated on, or has not yet completed its count.
6.2.4 Calibration Register
BADR1 + 6
This register controls all autocal operations. It is a Write-only register.
WRITE
CD0CD1CD2CD3CD4CD5CD6CD7SEL8800SEL8402SEL08CSRC0CSRC1CSRC2CALENSDI
0123456789101112131415
16