User`s manual

XTRCL
A write-clear to reset the
XTRIG
flip-flop.
1 = Clear
XTRIG
status.
0 = No Effect.
CHI_EN
These bits select the Analog Trigger/Gate Mode as described in Table 6-5 below.
CLO_EN
Note that the CHI Threshold is set by DAC1, CLO Threshold is set by DAC0.
HMODE
CHI >= CLO by definition.
Table 6-5. Analog Trigger/Gate Mode Selection Codes
WindowSignal goes high when within region defined by
CHI-CLO. Signal is low outside this region.
X11
Positive
Slope
Signal goes high when ATRIG is more positive than
CHI.
CLO has no effect.
X01
Negative
Slope
Signal goes high when ATRIG more negative than
CLO.
CHI has no effect.
X10
Positive
Hysteresis
Signal goes high when ATRIG is more negative than
CLO. Signal goes low when ATRIG becomes more
positive than CHI. Hysteresis level is the difference
between CHI and CLO.
100
Negative
Hysteresis
Signal goes high when ATRIG is more positive than
CHI. Signal goes low when ATRIG becomes more
negative than CLO. Hysteresis level is the difference
between CHI and CLO.
000
ModeAnalog Trigger/Gate FunctionHMODECLO_ENCHI_EN
ARM, FFM0
These bits work in conjunction the
PRTRG
bit during FIFO'd ADC operations. Refer to table 6-6. Note
that one FIFO = 512 samples.
15