User`s manual

Table 6-2. Offset/Range Configurations
19
µ
V
8
0 to 1.25V
111
38
µ
V
4
0 to 2.5V
011
76
µ
V
2
0 to 5V
101
153
µ
V
1
0 to 10V
001
38
µ
V
8
±
1.25V
110
76
µ
V
4
±
2.5V
010
153
µ
V
2
± 5V
100
305
µ
V
1
±
10V
000
Measurement
Resolution
Input GainInput RangeGS0GS1UNIBIP
ADPS[1:0]
These bits select the ADC Pacer Source. Maximum Internal/External Pacer frequency is
200 kHz (Table 6-3).
Table 6-3. ADC Pacer Source Coding
External Rising11
External Falling01
82C54 Counter/Timer10
SW Convert00
Pacer SourceADPS0ADPS1
Note: When ADPS[1:0] = 00, SW conversions are initiated via a word write to BADR2 + 0. Data is 'don't
care.'
READ
--------------EOC-
0123456789101112131415
EOC
Real-time, non-latched status of ADC End-of-Conversion signal.
1 = ADC DONE
0 = ADC BUSY
6.2.3 Trigger Control/Status Register
BADR1 + 4
This register provides control bits for all ADC trigger modes. It is a Read/Write register.
WRITE
TS0TS1TGPOLTGSELTGENBURSTEPRTRGXTRCLCLO_ENCHI_ENHMODEARMFFM0C0SRC--
0123456789101112131415
13