User`s manual

LADFUL
Status bit of ADC FIFO FULL status. This bit is latched.
1 = Indicates the ADC FIFO has exceeded full state. Data may have been lost.
0 = Indicates non-overflow condition of ADC FIFO.
DAEMI
Status bit of DAC FIFO Empty interrupt. Used to indicate that a FIFO'd DAC Operation
has completed.
1 = DAC FIFO Empty interrupt condition has occurred.
0 = DAC FIFO Empty interrupt condition has not occurred.
6.2.2 ADC Channel MUX And Control Register
BADR1 + 2
This register sets channel mux HI/LOA limits, ADC gain, offset and pacer source.
It is a Read/Write register.
WRITE
CHL1CHL2CHL4CHL8CHH1CHH2CHH4CHH8GS0GS1SEDIFFUNIBIPADPS0ADPS1--
0123456789101112131415
CHL8 - CHL1,
CHH8 - CHH1
When these bits are written, the analog input multiplexers are set to the channel specified by CHL8 -
CHL1. After each conversion, the input multiplexers increment to the next channel, reloading to the
"HL" start channel after the "CHI" stop channel is reached. LOA and HI channels are the decode of the
4-bit binary patterns.
GS[1:0]
These bits determine the ADC range as indicated below:
1.25V11
2.5V01
5V10
10V00
RangeGS0GS1
SEDIFF
Selects measurement configuration for the Analog Front-End.
1 = Sets Analog front-end to single-ended mode. This mode supports up to 16 channels.
0 = Sets Analog front-end to differential mode. This mode supports up to 8 channels.
UNIBIP
Selects offset configuration for the Analog Front-End.
1 = Analog Front-End Unipolar for selected range
0 = Analog Front-End Bipolar for selected range.
Table 6-2 summarizes all possible Offset/Range configurations:
12