User`s manual

6 REGISTER ARCHITECTURE
The PCI-DAS1602/16 operation registers are mapped into the PC I/O address space. Unlike its ISA
counterpart, this board has several base addresses each corresponding to a reserved block of addresses in
I/O space. Of six Base Address Regions (BADR) available in the PCI 2.1 specification, five are
implemented in this design and are summarized in Table 6-1 as follows:
Table 6-1. PCI-DAS1602/16 Register Summary
16-Bit WORDDAC Data, FIFO Clear RegistersBADR4
8-Bit BYTEPacer, Counter/Timer and DIO RegistersBADR3
16-Bit WORDADC Data, FIFO Clear RegistersBADR2
16-Bit WORDGeneral Control/Status RegistersBADR1
32-Bit DWORDPCI Controller Operation RegistersBADR0
OperationsFunctionI/O Region
BADRn will likely be different on different machines. Assigned by the PCI BIOS, these Base Address
values cannot be guaranteed to be the same even on subsequent power-on cycles of the same machine.
All software must interrogate BADR0 at run-time with a READ_CONFIGURATION_DWORD
instruction to determine the BADRn values.
Please see the "AMCC S5933 PCI Controller Data Book, Spring 1996" for more information.
6.1 BADR0
BADR0 is reserved for the AMCC S5933 PCI Controller operations. This region supports 32-bit
DWORD operations
6.2 BADR1
The I/O region defined by BADR1 contains 5 control and status registers for ADC, DAC, interrupt and
Autocal operations. This region supports 16-bit WORD operations.
6.2.1 Interrupt / ADC FIFO Register
BARD1 + 0
Interrupt Control, ADC status. A read/write register.
WRITE
INT0INT1INTEDAHFIEEOAIEDAHFCLEOACLINTCL----DAEMIEADFLCL
DAEMCL
-
0123456789101112131415
Write operations to this register allow the user to select interrupt sources, enable interrupts, clear
interrupts as well as ADC FIFO flags. The following is a description of the Interrupt/ADC FIFO
Register:
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