PCI-DAS1602/16 Multifunction Analog & Digital I/O Board User’s Manual Revision 3 August, 2001 © Copyright 2001, Measurement Computing Corporation
LIFETIME WARRANTY Every hardware product manufactured by Measurement Computing Corp. is warranted against defects in materials or workmanship for the life of the product, to the original purchaser. Any products found to be defective will be repaired or replaced promptly. LIFETIME HARSH ENVIRONMENT WARRANTYTM Any Measurement Computing Corp. product which is damaged due to misuse may be replaced for only 50% of the current price.
Table of Contents 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 SOFTWARE INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 HARDWARE INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.
This page is blank.
1 INTRODUCTION The PCI-DAS1602/16 is a multifunction measurement and control board designed to operate in computers with PCI bus accessory slots. The architecture of the boards is loosely based on the original CIO-DAS16; the standard of ISA bus data acquisition. New, denser connectors allow up to 100 signal lines where once 37 was the standard. The PCI-DAS1602/16 is easier to install and use than any previous DAS16.
2.2 HARDWARE INSTALLATION The PCI-DAS1602/16 employs a 100-pin connector. See Figure 2-1 below for the pinout.
2.3 CONNECTING SIGNALS TO THE PCI-DAS1602/16 Use a C100FF-2 cable to connect to the board. The cable has a pair of 50-pin ribbon cable legs joined together at a 100-pin header connector. You can use two CIO-MINI50 screw terminal boards to terminate field signals and route them into the PCI-DAS1602/16 with the C100FF-2 cable. Analog inputs to the PCI-DAS1602/16 can be connected in three different configurations; these are single-ended, floating-differential, and differential.
CAUTION Is that signal source really floating? Check it with a voltmeter before risking the PCI-DAS1602/16 and PC! If you can measure a constant voltage between the grounds of the PC and your signal source, it’s probably not floating. 2.4.3 Differential Proper measurement of a differential signal requires three wires from the signal source. The signals are Signal High (CH# High), Signal Low (CH# Low) and Signal Ground (Analog Ground).
3 Functional Overview FUNCTIONAL BLOCK DIAGRAM The PCI-DAS1602/16 is a multifunction measurement and control board. See Figure 3-1 below for a self-descriptive functional block diagram of the board. Figure 3-1.
4 SELF-CALIBRATION in the PCI-DAS1602/16 The PCI-DAS1602/16 provides self-calibration of the analog source and measure systems thereby eliminating the need for external equipment and user adjustments. All adjustments are made via 8-bit calibration DACs or digital potentiometers referenced to an on-board factory calibrated standard. The PCI-DAS1602/16 is shipped fully-calibrated from the factory with cal coefficients stored in nvRAM.
4.2 ANALOG OUTPUT CALIBRATION The analog output circuits are calibrated for both gain and offset. Coarse and Fine offset adjustments are made in the output buffer section. The tuning range of these adjustments allows for maximum DAC and output buffer offsets. Coarse and Fine gain calibration is performed via adjustments to the DAC reference. Note that there are no references associated with the DAC calibration - a fully calibrated ADC set to the respective DAC range is used as the measurement system.
5 PROGRAMMING & APPLICATIONS Although the PCI-DAS1602/16 is part of the larger DAS family, there is no correspondence between registers. Software written at the register level for the other DAS's will not work with the PCI-DAS1602/16. This includes any driver or library where the target board is other than a PCI-DAS1602/16. 5.1 PROGRAMMING LANGUAGES The Universal Library provides complete access to the PCI-DAS1602/16 functions from a range of programming languages; both DOS and Windows.
6 REGISTER ARCHITECTURE The PCI-DAS1602/16 operation registers are mapped into the PC I/O address space. Unlike its ISA counterpart, this board has several base addresses each corresponding to a reserved block of addresses in I/O space. Of six Base Address Regions (BADR) available in the PCI 2.1 specification, five are implemented in this design and are summarized in Table 6-1 as follows: Table 6-1.
INT[1:0] General Interrupt Source selection bits. INT1 INT0 Source 0 0 External 0 1 End of Channel Scan 1 0 AD FIFO Half Full 1 1 AD FIFO Not Empty INTE Enables interrupt source selected via the INT[1:0] bits. 1 = Selected interrupt Enabled. 0 = Selected interrupt Disabled DAHFIE Enables DAC FIFO Half-Full signal as an interrupt source. Used for high speed DAC operations. 1= Enable DAC FIFO Half-Full interrupt.
Interrupt Control, ADC status. A read/write register. READ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - DAEMI LADFUL ADNE ADNEI ADHFI EOBI XINTI INT EOAI DAHFI - - - - - Write operations to this register allow you to check status of the selected interrupts and ADC FIFO flags. The following is a description of Interrupt / ADC FIFO Register Read bits: DAHFI Status bit of DAC FIFO Half-Full interrupt 1 = Indicates a DAC FIFO Half-Full interrupt has been latched.
LADFUL Status bit of ADC FIFO FULL status. This bit is latched. 1 = Indicates the ADC FIFO has exceeded full state. Data may have been lost. 0 = Indicates non-overflow condition of ADC FIFO. DAEMI Status bit of DAC FIFO Empty interrupt. Used to indicate that a FIFO'd DAC Operation has completed. 1 = DAC FIFO Empty interrupt condition has occurred. 0 = DAC FIFO Empty interrupt condition has not occurred. 6.2.
Table 6-2. Offset/Range Configurations UNIBIP GS1 GS0 Input Range Input Gain Measurement Resolution 0 0 0 ±10V 1 305µV 0 0 1 ± 5V 2 153µV 0 1 0 ±2.5V 4 76µV 0 1 1 ±1.25V 8 38µV 1 0 0 0 to 10V 1 153µV 1 0 1 0 to 5V 2 76µV 1 1 0 0 to 2.5V 4 38µV 1 1 1 0 to 1.25V 8 19µV ADPS[1:0] These bits select the ADC Pacer Source. Maximum Internal/External Pacer frequency is 200 kHz (Table 6-3). Table 6-3.
TS[1:0] These bits select one-of-three possible ADC Trigger Sources (Table 6-4): Table 6-4. ADC Trigger Sources TS1 TS0 Source 0 0 Disabled 0 1 SW Trigger 1 0 External (Digital) 1 1 External (Analog) Note: TS[1:0] should be set to 0 while setting up Pacer source and count values. TGPOL This bit sets the polarity for the external trigger/gate. Internally, the ADC is triggered on a rising edge or gated on with an active high signal.
A write-clear to reset the XTRIG flip-flop. 1 = Clear XTRIG status. 0 = No Effect. XTRCL CHI_EN These bits select the Analog Trigger/Gate Mode as described in Table 6-5 below. CLO_EN Note that the CHI Threshold is set by DAC1, CLO Threshold is set by DAC0. HMODE CHI >= CLO by definition. Table 6-5. Analog Trigger/Gate Mode Selection Codes CHI_EN CLO_EN HMODE Analog Trigger/Gate Function Mode 0 0 0 Signal goes high when ATRIG is more positive than CHI.
Table 6-6. FIFO'd ADC Operations PRTRG FFM0 ARM is set... FIFO Mode 0 0 Via SW when remaining count < one FIFO -----------------------Via SW immediately # Samples >1 FIFO Normal Mode ---------------------------------1/2 FIFO < # Samples < one FIFO Normal Mode 0 1 1 0 1 1 C0SRC Via SW immediately Sample CTR Starts on...
CD[7:0] These 8 bits are the D/A code inputs for the analog-front DAC08 offset calibration DAC. Complimentary current outputs of the DAC08 are equal at mid-scale, 7Fh. This should be the default, non-calibrated value. SEL8800 This bit enables the 8-bit trim DACs for the following circuits (Table 6-7): Table 6-7.
CALEN This bit is used to enable Cal Mode. 1 = Selected Cal Source, CSRC[2:0], is fed into Analog Channel 0. 0 = Analog Channel 0 functions as normal input. SDI Serial Data In. This bit is used to set serial address/data stream for the DAC8800 TrimDac and 8402 digital potentiometer. Used in conjunction with SEL8800 and SEL8402 bits. 6.2.5 DAC Control/Status Register BADR1 + 8 This register selects the DAC gain/range, Pacer source, trigger and High-Speed Modes.
These bits select the High-Speed DAC Modes as follows (Table 6-11): HS[1:0] Table 6-11. High-Speed DAC Modes Select Codes DACnR[1:0] HS1 HS0 DAC Mode 0 0 Disabled 0 1 DAC0 1 0 DAC1 1 1 Simultaneous DAC0/1 These bits select the independent gains/ranges for either DAC0 or DAC1. n=0 for DAC0 and n=1 for DAC1 (Table 6-12). Table 6-12.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 MSB AD[15:0] LSB This register contains the current ADC data word. Data format is dependent upon offset mode: Bipolar Mode: Offset Binary Coding 0000 h = −FS 7FFFh = Mid-scale (0V) FFFFh = +FS − 1 LSB Unipolar Mode: Straight Binary Coding 0000 h = −FS (0V) 7FFFh = Mid-scale (+FS/2) FFFFh = +FS − 1 LSB 6.3.2 ADC FIFO Clear Register BADR2 + 2 ADC FIFO Clear register.
6.4.1 ADC Pacer Clock Data And Control Registers 8254A COUNTER 0 DATA - ADC RESIDUAL SAMPLE COUNTER BADR3 + 0 READ/WRITE 7 6 5 4 2 3 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Counter 0 is used to stop the acquisition when the desired number of samples have been gathered. It is gated on when a 'residual' number of conversions remain. Counter 0 will be enabled by use of the ARM bit (BADR1 + 4). Counter 0 is to operated in Mode 0.
6.4.2 High-Drive Digital I/O Data and Control Registers The 24 High-Drive DIO lines are grouped as three byte-wide I/O ports. Port assignment and functionality is identical to that of the industry standard 8255 Peripheral Interface operating in Mode 0. Please see the Intel or Harris data sheets for more information. Drive capability of each line is 15 mA in the TTL HI state and 24 mA in the TTL LOA state. HDIO PORT A DATA BADR3 + 4 PORT A can be configured as an 8-bit I/O channel.
The following table contains codes for the possible I/O Port configurations for the HDIO: Table 6-14.
8254B COUNTER 1 DATA - DAC PACER DIVIDER LOWER BADR3 + 9 READ/WRITE 7 6 5 4 2 3 1 0 D7 D6 D5 D4 D3 D2 D1 D0 8254B COUNTER 2 DATA - DAC PACER DIVIDER UPPER BADR3 + Ah READ/WRITE 7 6 5 4 2 3 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Counter 1 provides the lower 16 bits of the 32-bit pacer clock divider. Its output is fed to the clock input of Counter 2 which provides the upper 16-bits of the pacer clock divider. The clock input to Counter 1 is a precision 10 MHz oscillator source.
6.5 BADR4 The BADR4 contains the shared DAC data register and the DAC FIFO clear register. 6.5.1 DAC Data Register BADR4 + 0 DAC Data register. A Write-only register. WRITE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 MSB DA[15:0] LSB These bits represent the DAC data word.
Table 6-15. Target DAC Selection Codes HS1 HS0 SELECTED DAC(S) LOCATION # FIFO DATA 0 0 None N/A N/A 0 1 DAC0 0 1 2 3 | DAC0 DAC0 DAC0 DAC0 | 1 0 DAC1 0 1 2 3 | DAC1 DAC1 DAC1 DAC1 | 1 1 DAC0 & DAC1 0 1 2 3 | DAC0 DAC1 DAC0 DAC1 | NOTE: FIFO location #0 is the first value written to the Cleared DAC FIFO. 6.5.2 DAC FIFO Clear Register BADR4 + 2 DAC FIFO Clear register. A Write-only register. A write to this address location clears the DAC FIFO. Data is don't care.
7 SPECIFICATIONS Typical for 25 DegC unless otherwise specified. Analog Input Section A/D converter type Resolution Programmable ranges A/D pacing Data transfer Bust mode Polarity Number of channels Interrupts Interrupt enable AD976ABN 16 bits ±10V, ±5V, ±2.5V, ±1.25V, 0 to 10V, 0 to 5V, 0 to 2.5V, 0 to 1.
Analog Outputs: Resolution Number of channels D/A type Voltage Ranges Offset error Gain error Differential nonlinearity Integral nonlinearity Monotonicity D/A Gain drift D/A Bipolar offset drift D/A Unipolar offset drift Output Coupling Amp Output Impedance 16 bits 2 AD669BR ±10V, ±5V, 0 to 5V, 0 to 10V. Independently-selectable between channels. ±100uV max, all ranges (calibrated) ±30.5 ppm max (calibrated) ±1 LSB max ±1 LSB max 16 bits at 25 DegC ±15 ppm/°C max ±5 ppm/°C max ±3 ppm/°C max DC 0.
Counter Section Counter type Configuration 82C54 Two 82C54 devices. three down-counters per 82C54, 16 bits each 82C54A: (Counters #1, 2, & 3) Counter 0 - ADC residual sample counter. Source: ADC Clock. Gate: Programmable source. Output: End-of-Acquisition interrupt. Counter 1 - ADC Pacer Lower Divider Source: 10 MHz oscillator Gate: Tied to Counter 2 gate, programmable source. Output: Chained to Counter 2 Clock. Counter 2 - ADC Pacer Upper Divider Source: Counter 1 Output.
For Your Notes.
EC Declaration of Conformity We, Measurement Computing Corp.
Measurement Computing Corporation 16 Commerce Boulevard, Middleboro, Massachusetts 02346 (508) 946-5100 Fax: (508) 946-9500 E-mail: info@measurementcomputing.com www. measurementcomputing.
