User`s manual

USER COUNTER CLOCK CONTROL
BADR3 + 0Ch
READ/WRITE
CTR1_CLK_SELXXXXXXX
01234567
CTR1 _CLK_SEL = 1. The onboard 100 kHz clock signal is ANDed with the COUNTER 1 CLOCK
INPUT (pin 21). A high on pin 21 will allow pulses from the onboard source
into the 8254 Counter 1 input. (This input has a pull-up resistor on it, so no
connection is necessary to use the onboard 100 kHz clock.
CTR1_CLK_SEL = 0, The input to 8254 Counter 1 is entirely dependent on pulses at pin 21, COUNTER
1 CLOCK INPUT.
RESIDUAL SAMPLE COUNTER REGISTERS
BADR3 + 0Dh
READ/WRITE
D0D1D2D3D4D5D6D7
01234567
BADR3 + 0Eh
READ/WRITE
D8D9XXXXXX
01234567
The residual count, data bits D9:D0 are used to specify the number of samples at the end of a paced
acquisition that will be collected before the EOA (end of acquisition) interrupt is generated. This is
useful when the total number of samples is not a multiple of half the FIFO size (512) or the total number
of samples is less than the FIFO size (1024).
Always write the residual count before setting the EOA_INT_SEL bit. Writing to either register will
reset the counter with the new values. You must write the values each acquisition even if they have not
changed. Use the following rules for correct operation.
Total number of samples is less than 512
1. Before you start the acquisition, write the total number of samples to the residual counter, an 87h to
BADR3+4 ( INTE, EOA_INT_SEL, and FIFO_HALF FULL enabled), and a 67h to BADR1+4Ch
(INTE and PCINTE enabled).
2. Start the acquisition
3. The first interrupt you get will be the EOA interrupt. First clear the EOA_INT_SEL bit (bit 2
BADR3+4). Then read 20 samples from FIFO. The last thing you should do in your interrupt
service routine is to clear the INT bit (bit 6, BADR3+4) and disable interrupts by writing a “0” to the
INTE bit (bit 7, BADR3+4).
EXAMPLE: 20 total samples
1. Before you start the acquisition, write a 20 to the residual counter, an 87h to BADR3+4, and a 67h
to BADR1+4Ch
2. Start the acquisition.
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