User`s manual

GATE_POL = 1, the trigger / gate polarity is set to negative-going edge / low level for non burst mode
and positive-going edge / high level for burst mode
GATE_POL = 0, the trigger / gate polarity is set to positive-going edge / high level for non burst mode
and negative-going edge / low level for burst mode
on a read, GATE_STATUS = 1, the gate to the internal pacer is on.
GATE_STATUS = 0, the gate to the internal pacer is off.
on a write, GATE_STATUS = 0 clears the hardware latch when LATCH = 1
BURST MODE and CONVERTER CONTROL
BADR3 + 6
READ/WRITE
CONV_ENBMEXXXXXX
01234567
CONV_EN = 1, Conversions are enabled
CONV_EN = 0, Conversions are disabled
BME = 1, Bursting is enabled. When burst mode is enabled, the mux channel select bits in BADR3+0
are used to specify the channels in the burst.
BME = 0, Bursting is disabled
The burst mode generator is a clock signal that paces the A/D at the maximum multi-channel sample rate,
then periodically, performs additional maximum rate scans. In this way, the channel to channel skew
(time between successive samples in a scan) is minimized without taking a large number of undesired
samples (Figure 6-1).
.
Figure 6-1. Burst Mode Timing
The PCIM-DAS1602/16 burst mode generator takes advantage of the fast A/D. The burst mode skew is
10 µs between channels for the PCIM-DAS1602/16. It is 13.3 µs for the CIO-DAS1602/16
27
Ch0 Ch1 Ch2 Ch3
Ch0 Ch1 Ch2 Ch3
10
µ
s
Delay
Burst mode pacer fixed at 10
µ
s
The length of the delay between bursts is set by one of the
Internal counters or m ay be controlled via external trigger