User`s manual

6.4 BADR3 REGISTERS
Residual Counter lower byte
BADR3 + 0Eh
Residual Counter upper 2 bits
BADR3 + 0Dh
User Counter Clock ControlUser Counter Clock Setting
BADR3 + 0Ch
82C54 Counter Control Data82C54 Counter Control Data
BADR3 + 0Bh
82C54 Counter 3 Data82C54 Counter 3 Data
BADR3 + 0Ah
82C54 Counter 2 Data82C54 Counter 2 Data
BADR3 + 9
82C54 Counter 1 Data82C54 Counter 1 Data
BADR3 + 8
Programmable Gain ControlProgrammable Gain Settings
BADR3 + 7
Burst Mode and Converter ControlBurst Mode and Converter Settings
BADR3 + 6
A/D Pacer Clock ControlA/D Pacer Clock Settings
BADR3 + 5
Interrupt ControlInterrupt Settings /Status
BADR3 + 4
ADC Conversion Status
BADR3 + 3
ADC Channel Status and Switch Settings
BADR3 + 2
Main Connector Digital OutputsMain Connector Digital Inputs
BADR3 + 1
Mux scan limitsMux scan limits
BADR3 + 0
WRITE FUNCTIONREAD FUNCTION
REGISTER
MUX SCAN LIMITS REGISTER
BADR3 + 0
READ/WRITE
CH L0CH L1CH L2CH L3CH H0CH H1CH H2CH H3
01234567
READ
The current channel scan limits are read as one byte. The high channel number scan limit is in the
most
significant four bits. The low channel scan limit is in the
least
significant four bits.
WRITE
The channel scan limits desired are written as one byte. The high channel number scan limit is in the
most
significant four bits. The low channel scan limit is in the
least
significant four bits.
Every write to this register sets the current A/D channel MUX setting to the number in
bits 0-3 and resets the FIFO. You should delay 10
µ
s after setting the MUX (to allow for
settling time) before initiating a conversion.
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