User`s manual

Unipolar Mode: Straight Binary Coding
0000 h = −FS (0V)
7FFFh = Mid-scale (+FS/2)
FFFFh = +FS − 1LSB
WRITE
Writing to this register is only valid for SW initiated conversions. The ADC Pacer source must
be set to software polled (see BADR3 + 5). A null write to BADR2 + 0 will begin a single conversion.
Conversion status may be determined by polling the EOC bit in BADR3 + 2.
BADR2 + 2
DAC 0 Data
WRITE ONLY
DA0DA1DA2DA3DA4DA5DA6DA7DA8DA9DA10DA11xxxx
0123456789101112131415
MSB LSB
BADR2 + 4
DAC 1 Data
WRITE ONLY
DA0DA1DA2DA3DA4DA5DA6DA7DA8DA9DA10DA11xxxx
0123456789101112131415
MSB LSB
DA[11:0]
These bits represent the DAC data word. Format is dependent upon offset mode as described below:
+/-10V Range, Vref = −10V
+/-5V Range, Vref = −5V
Bipolar Mode: Offset Binary Coding
000 h = Vref
7FFh = Mid-scale
(0V)
FFFh = −Vref − 1 LSB, Vref <0V
= −Vref + 1 LSB, Vref >0V
Unipolar Mode: Straight Binary Coding
000 h = 0
V
7FFh = Mid-scale (−Vref/2)
FFFh = −Vref − 1 LSB, Vref <0V
= −Vref + 1 LSB, Vref >0V
On power up and system reset, the DACs’ outputs are disabled and set to 0V. The first write to each
DAC will enable that DAC.
The DACs ranges are jumper-settable in hardware. The settings are not software-readable.
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