User`s manual

LINTE = 1, on the local side interrupt is enabled

LINTE = 0, on the local side interrupt is disabled

the INT bit is read only

INT = 1, interrupt is active

INT = 0, interrupt is not active

PCINTE = 1, on the PCI side, the interrupt is enabled

PCINTE = 0, on the PCI side, the interrupt is disabled

You must set both PCINTE and LINTE to 1 to enable interrupts. There is also an interrupt enable bit

(INTE) in BADR3+4. This bit must also be set to 1 to enable interrupts.

This register is only used to enable the local and PCI interrupt bits so the interrupt generated by the on

board logic can propagate through the PCI-9052 interface to the PCI bus INTA. The interrupts are not

cleared in this register. The board has both edge and level sensitive interrupts. The edge sensitive

interrupts, EndOfAcquisition, EndOfBurst, and EndOfConversion must be cleared by writing a 0 to the

INT bit in BADR3+4. This must be done at the end of your interrupt service routine. The level sensitive

interrupts, FifoHalfFull and FifoNotEmpty, will be regenerated after you service the interrupt if their

condition is still true. See the section on BADR3+4 for more details.

6.3 BADR2 REGISTERS

DAC 1 Datanone

BADR2 + 4

DAC 0 Datanone

BADR2 + 2

Begin single conversionADC Data

BADR2 + 0

WRITE FUNCTIONREAD FUNCTION

The I/O Region defined by BADR2 contains the 16-bit ADC data and the two 12-bit DAC data registers.

BADR2 + 0

ADC Data/Convert.

READ

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15

0123456789101112131415

MSB LSB

AD[15:0]

This register contains the current ADC data word. Data format is dependent upon offset mode:

Bipolar Mode: Offset Binary Coding

0000 h = −FS

7FFFh = Mid-scale

(0V)

FFFFh = +FS − 1LSB