User`s manual

INTERRUPTS
Table 12. Interrupts
External (rising TTL edge event)
Residual sample counter
A/D end of conversion
A/D end of channel scan
A/D FIFO-not-empty
A/D FIFO-half-full
D/A FIFO-not-empty
D/A FIFO-half-full
Interrupt sources
Programmable PCI Interrupt enable
INTA# - mapped to IRQn via PCI BIOS at boot-timeInterrupt
COUNTER SECTION
Table 13. Counters
Chained to Counter 6 clockCounter 5 Output
Tied to Counter 6 gate, programmable source.Counter 5 Gate
Internal 10 MHz Counter 5 Source
Counter 5
–
DAC pacer lower divider
Available at 100 pin connector (OUT 4)Counter 4 Output
User input at 100 pin connector (GATE 4)Counter 4 Gate
User input at 100 pin connector (CLK 4) or internal
10 MHz (software selectable)
Counter 4 Source
Counter 4
-
(Non pre-trigger Mode)
End-of-Acquisition interrupt sourceCounter 4 Output
A/D External Trigger Counter 4 Gate
ADC Clock Counter 4 Source
Counter 4 (Pre-trigger Mode)
ADC Pacer clock (if software selected), available at user
connector
Counter 3 Output
Tied to Counter 2 gate, programmable sourceCounter 3 Gate
Counter 2 OutputCounter 3 Source
Counter 3
-
ADC pacer upper divider
Chained to Counter 3 clockCounter 2 Output
Tied to Counter 3 gate, programmable source.Counter 2 Gate
Internal 10 MHz Counter 2 Source
Counter 2
-
ADC pacer lower divider
End-of-Acquisition interrupt sourceCounter 1 Output
Programmable source Counter 1 Gate
ADC Clock Counter 1 Source
Counter 1
–
ADC residual sample
counter
Two 82C54 devices. 3 down-counters per 82C54, 16 bits
each
Configuration
82C54Counter type
41