User`s manual

Table 9 – Accuracy Components (errors in LSBs)
±1.0 max±1.0 max±0.4 max±2.0 max0 to +5.000V
±1.0 max±1.0 max±0.2 max±2.0 max0 to +10.00V
±1.0 max±1.0 max±0.2 max±2.0 max±5.000V
±1.0 max±1.0 max±0.1 max±2.0 max±10.00V
ILE (LSB)DLE (LSB)Offset Error (LSB)Gain Error (LSB)Range
Each PCI-DAS1602/12 is tested at the factory to assure the board’s overall error does not exceed ±3.0
LSB.
Total board error is a combination of Gain, Offset, Integral Linearity and Differential Linearity error. The
theoretical worst-case error of the board may be calculated by summing these component errors. Worst
case error is realized only in the unlikely event that each of the component errors are at their maximum
level, and causing error in the same direction. Although an examination of the chart and a summation of the
maximum theoretical errors shows that the board could theoretically exhibit a ±4.4 LSB error, our testing
assures this error is never realized in a board that we ship.
ANALOG OUTPUT PACING AND TRIGGERING
Table 10. Analog Output Pacing and Triggering Summary
250 kHz max per channel, 2 channels simultaneousThroughput
Update DACs individually or simultaneously (SW selectable)
Programmed I/O
From 1024 sample FIFO via REPOUTSW mode. Data
interleaved for dual analog output mode.
Data transfer
Software triggered
External digital (External D/A Pacer Gate)D/A trigger Modes
Software paced
External source (D/A External Pacer)
Internal counter D/A pacing
(SW programmable)
DIGITAL INPUT / OUTPUT
Table 11. Digital Input/Output
Input mode (high impedance)Power-up / reset state
0.4V maxOutput low voltage (IOL = 2.5 mA)
3.0V min
Output high voltage (IOH = −2.5 mA)
0.8V max, –0.5V absolute minInput low voltage
2.0V min, 5.5V absolute maxInput high voltage
2 banks of 8 with handshake
3 banks of 8 or
2 banks of 8 and 2 banks of 4 or
Configuration
24 (Port A0 through Port C7)Number of I/O
82C55Digital Type 82C55
40