User`s manual

7.6.1 DAC DATA REGISTER
BADR4 + 0
DAC Data register. A Write-only register.
WRITE
DA0DA1DA2DA3DA4DA5DA6DA7DA8DA9DA10DA110000
0123456789101112131415
MSB LSB
DA[11:0]
These bits represent the DAC data word. Format is dependent upon offset
mode as described below:
Bipolar Mode: Offset Binary Coding
000 h = −FS
7FFh = Mid-scale
(0V)
FFFh = +FS − 1LSB
Unipolar Mode: Straight Binary Coding
000 h = −FS (0V)
7FFh = Mid-scale (+FS/2)
FFFh = +FS − 1LSB
Paced DAC operations require that the FIFO be loaded with the appropriate data. A REP OUTSW
instruction to this address will do this. It is important to note that the FIFO is the shared data source
between DAC0 and DAC1. Take care to ensure that DAC0 data always precedes DAC1 data during
simultaneous operations. Target DAC selection is made via the
HS[1:0]
bits described earlier.
DAC0
DAC1
DAC0
DAC1
0
1
2
3
DAC0 and DAC111
DAC1
DAC1
DAC1
DAC1
0
1
2
3
DAC101
DAC0
DAC0
DAC0
DAC0
0
1
2
3
DAC010
N/AN/ANone00
FIFO DATALOCATION #SELECTED DAC(S)HS0HS1
NOTE
: FIFO location #0 is the first value written to the Cleared DAC FIFO.
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