User`s manual

8254B COUNTER 1 DATA
- DAC PACER DIVIDER LOWER
BADR3 + 9
READ/WRITE
D0D1D2D3D4D5D6D7
01324567
8254B COUNTER 2 DATA
- DAC PACER DIVIDER UPPER
BADR3 + Ah
READ/WRITE
D0D1D2D3D4D5D6D7
01324567
Counter 1 provides the lower 16 bits of the 32-bit pacer clock divider. Its output is fed to the clock input of
Counter 2 which provides the upper 16-bits of the pacer clock divider. The clock input to Counter 1 is a
precision 10 MHz oscillator source.
Counter 2's output is called the 'Internal Pacer' and can be selected by software to the be the ADC Pacer
source. Configure Counters 1 & 2 to operate in 8254 Mode 2.
8254B CONTROL REGISTER
BADR3 + Bh
WRITE ONLY
D0D1D2D3D4D5D6D7
01324567
The control register is used to set the operating Modes of 8254B Counters 0,1, and 2. A counter is config-
ured by first writing mode information to the Control Register, then count data is written to the specific
Counter Register.
The Counters on the 8254 are 16-bit devices. Since the interface to the 8254 is eight bits wide, Count data
is written to the Counter Register as two successive bytes; first the low byte, then the high byte.
The Control Register is eight bits wide. Further information can be obtained from Intel or Harris or our
WEB site at http://www.computerboards.com/PDFmanuals/82C54.pdf
7.6 BADR4
The I/O Region defined by BADR4 contains the shared DAC data register and the DAC FIFO clear
register.
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