User`s manual

8254A COUNTER 2 DATA
- ADC PACER DIVIDER UPPER
BASE + 2
READ/WRITE
D0D1D2D3D4D5D6D7
01324567
Counter 1 provides the lower 16 bits of the 32-bit pacer clock divider. Its output is tied to the clock input
of Counter 2 which provides the upper 16-bits of the pacer clock divider. The clock input to Counter 1 is a
precision 10 MHz oscillator source.
Counter 2 output is called the 'Internal Pacer' and can be selected by software to be the ADC Pacer source.
Configure Counters 1 and 2 to operate in 8254 Mode 2.
ADC 8254 CONTROL REGISTER
BADR3 + 3
WRITE ONLY
D0D1D2D3D4D5D6D7
01324567
The control register is used to set the operating Modes of 8254 Counters 0,1 & 2. A counter is configured
by writing the correct Mode information to the Control Register followed by count written to the specific
Counter Register.
The Counters on the 8254 are 16-bit devices. Since the interface to the 8254 is only 8-bits wide, Count
data is written to the Counter Register as two successive bytes. First the low byte is written, then the high
byte. The Control Register is eight bits wide. Further information can be obtained from Intel or Harris or
our WEB site at http://www.computerboards.com/PDFmanuals/82C54.pdf
7.5.2 DIGITAL I/O DATA AND CONTROL REGISTERS
The 24 DIO lines on the PCI-DAS1602/12 are grouped as three, byte-wide I/O ports. Port assignment and
functionality is the industry-standard 82C55 Peripheral Interface. For more information, contact Intel or
Harris or call our WEB site at http://www.computerboards.com/PDFmanuals/82C55A.pdf
DIO PORT A DATA
BADR3 + 4
PORT A can be configured as an 8-bit input or output channel.
READ/WRITE
31