User`s manual

DAPS[1:0]

These bits select the DAC Pacer Source:

External Rising Edge11

External Falling Edge01

Internal 82C54

Programmed via BADR3 + 9, + A

SW Convert00

Pacer SourceDAPS0DAPS1

HS[1:0]

These bits select the High-Speed DAC Modes as follows:

Simultaneous DAC0/111

DAC101

DAC0

Disabled00

DAC ModeHS0HS1

DACnR[1:0]

These bits select the independent gains/ranges for either DAC0 or DAC1.

n=0 for DAC0 and n=1 for DAC1.

2.44mVUnipolar 10V11

1.22mVUnipolar 5V01

4.88mVBipolar 10V10

2.44mVBipolar 5V00

LSB SizeRangeDACnR0DACnR1

READ

LDAEM---------------

0123456789101112131415

LDAEM

This is the latched version of the DAC FIFO_EMPTY signal. This bit must

be write-write cleared with the

DAEMCL

bit.

1 = DAC FIFO was emptied at some point during FIFO'd operations. Incorrect data may

have been clocked into the selected DAC(s).

0 = DAC FIFO did not empty during FIFO'd operations. Status good.