User`s manual

CSRC[2:0]
These bits select the different calibration sources available to the ADC front end.
VDAC1111
VDAC0011
8.6mV101
0.875V001
1.75V110
3.5V010
7.0V100
AGND000
Cal SourceCSRC0CSRC1CSRC2
CALEN
This bit is used to enable Cal Mode.
1 = Selected Cal Source,
CSRC[2:0]
, is fed into Analog Channel 0.
0 = Analog Channel 0 functions as normal input.
SDI
Serial Data In. This bit is used to set serial address/data stream for the DAC8800
TrimDac and 7376 digital potentiometer. Used in conjunction with
SEL8800
and
SEL7376
bits.
7.3.5 DAC CONTROL/STATUS REGISTER
BADR1 + 8
This register selects the DAC gain/range, Pacer source, trigger and High-Speed Modes. In addition, DAC
FIFO status information is available. This is a Read/Write register.
WRITE
LDAEMCLDACENSTARTDAPS0DAPS1HS0HS1-DAC0R0DAC0R1DAC1R0DAC1R1----
0123456789101112131415
LDAEMCL
This is a Write-clear bit to reset the latched EMPTY status flag of the DAC FIFO.
1 = Reset Empty Flag
0 = No Effect.
DACEN
This bit enables the Analog Out features of the board.
1 = DAC0/1 enabled.
0 = DAC0/1 disabled.
START
This bit starts FIFO'd DAC operations. If used with
DAXTRG
, the external trigger
signal, the
START
bit is used to arm the operation.
1 = Start/Arm FIFO operations.
0 = Disable FIFO'd DAC operations.
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