User`s manual

0 = No Effect.
HI_EN,
These bits select the Analog Trigger/Gate Mode as described in the table below.
CLO_EN,
Note that the CHI Threshold is set by DAC1, CLO Threshold is set by DAC0.
HMODE
CHI >= CLO by definition.
WindowSignal goes high when within region defined by
CHI-CLO. Signal is low outside this region.
X11
Positive
Slope
Signal goes high when ATRIG is more positive
than CHI.
CLO has no effect.
X01
Negative
Slope
Signal goes high when ATRIG more negative
than CLO.
CHI has no effect.
X10
Positive
Hysteresis
Signal goes HIGH when ATRIG is more negative
than CLO. Signal goes low when ATRIG
becomes more positive than CHI. Hysteresis
level is the difference between CHI and CLO.
100
Negative
Hysteresis
Signal goes HIGH when ATRIG is more positive
than CHI. Signal goes low when ATRIG
becomes more negative than CLO. Hysteresis
level is the difference between CHI and CLO.
000
ModeAnalog Trigger/Gate FunctionHMODECLO_ENCHI_EN
ARM,
FFM0
These bits works in conjunction with
PRTRG
during FIFO'd ADC operations.
The table below provides a summary of bit settings and operation.
XTRIG
# Samples <1/2 FIFO,
Pre-Trigger Mode
Via SW immediately
11
ADHF
# Samples >1 FIFO
Pre-Trigger Mode
----------------------------------
1/2 FIFO < # Samples < 1
FIFO
Pre-Trigger Mode
Via SW when
remaining count
<1024
------------------------
Via SW immediately
01
ADC Pacer
# Samples <1/2 FIFO
Normal Mode
Via SW immediately
10
ADHF
# Samples >1 FIFO
Normal Mode
----------------------------------
1/2 FIFO < # Samples < 1
FIFO
Normal Mode
Via SW when
remaining count
<1024
------------------------
Via SW immediately
00
Sample CTR
Starts on...
FIFO ModeARM
is set...
FFM0PRTRG
25