User`s manual

TS[1:0]
These bits select one-of-three possible ADC Trigger Sources:
External (Analog)11
External (Digital)01
Software Trigger10
Disabled00
SourceTS0TS1
Note: TS[1:0] should be set to 0 while setting up Pacer source and count values.
TGPOL
This bit sets the polarity for the external trigger/gate. Internally, the ADC is triggered on
a rising edge or gated on with an active high signal. Use
TGPOL
to condition external
trigger/gate for proper polarity.
1 = External trigger/gate input inverted.
0 = External trigger/gate input not inverted.
TGSEL
This bit selects whether external ADC control signal is an edge or a level. Use
TGPOL
signal to create rising edge or high level input.
1 = Edge triggered.
0 = Level triggered.
TGEN
This bit is used to enable External Trigger/Gate function
1 = Selected Trigger Source enabled.
0 = Selected Trigger Source has no effect.
Note that external trigger/gate requires proper setting of the
TS[1:0]
,
TGPOL
,
TGSEL
and
TGEN
bits.
Example: Application requires use of external falling edge to start acquisition. Set:
TS1 = 1, TS0 = 0 -> External Digital Trigger
TGPOL = 1 -> Invert falling edge
TGSEL = 1 -> Edge Triggered event
TGEN = 1 -> Enable External Trigger.
After
TGEN
is set, the next falling edge will start a paced ADC
conversion. Subsequent triggers will have no effect until the external
trigger flop is cleared (
XTRCL
).
BURSTE
This bit enables ADC Burst mode. Start/Stop channels are selected via the CHLx,
CHHx bits in ADC CTRL/STAT register at BADR1 + 2.
1 = Burst Mode enabled
0 = Burst Mode disabled
PRTRG
This bit enables ADC Pre-trigger Mode. This bit works with the ARM and FFM0 bits
when using Pre-trigger mode.
1 = Enable Pre-trigger Mode
0 = Disable Pre-trigger Mode
XTRCL
A write-clear to reset the
XTRIG
flip-flop.
1 = Clear
XTRIG
status.
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