User`s manual

305 µV8

0 to 1.25 V

111

610 µV4

0 to 2.5 V

011

1.22 mV2

0 to 5 V

101

2.44 mV1

0 to10 V

001

610 µV8

1.25 V110

1.22 mV4

2.5 V010

2.44 mV2

5 V

100

4.88 mV1

10 V000

Measurement

Resolution

Input GainInput RangeGS0GS1UNIBIP

ADPS[1:0]

These bits select the ADC Pacer Source. Maximum Internal/External Pacer

frequency is 330 kHz.

External Rising11

External Falling01

82C54 Counter/Timer10

Software Convert00

Pacer SourceADPS0ADPS1

Note: For ADPS[1:0] = 00 case, software conversions are initiated

via a word write to BADR2 + 0. Data is 'don't care.'

READ

--------------EOC-

0123456789101112131415

EOC

Real-time, non-latched status of ADC End-of-Conversion signal.

1 = ADC DONE

0 = ADC BUSY

7.3.3 TRIGGER CONTROL/STATUS REGISTER

BADR1 + 4

This register provides control bits for all ADC trigger modes. A Read/Write register.

WRITE

TS0TS1TGPOLTGSELTGENBURSTEPRTRGXTRCLCLO_ENCHI_ENHMODEARMFFM0C0SRC--

0123456789101112131415