User`s manual

0 = Indicates non-overflow condition of ADC FIFO.
DAEMI
Status bit of DAC FIFO Empty interrupt. Used to indicate that a FIFO'd DAC
operation has completed.
1 = DAC FIFO Empty interrupt condition has occurred.
0 = DAC FIFO Empty interrupt condition has not occurred.
7.3.2 ADC CHANNEL MUX AND CONTROL REGISTER
BADR1 + 2
This register sets channel MUX HI/LO limits, ADC gain, offset and pacer source.
A Read/Write register.
WRITE
CHL1CHL2CHL4CHL8CHH1CHH2CHH4CHH8GS0GS1SEDIFFUNIBIPADPS0ADPS1--
0123456789101112131415
CHL8-CHL1,
CHH8-CHH1
When these bits are written, the analog input multiplexers are set to the channel
specified by CHL8-CHL1. After each conversion, the input multiplexers increment to
the next channel, reloading to the "CHL" start channel after the "CHH" stop channel is
reached. LO and HI channels are the decode of the 4-bit binary patterns.
GS[1:0]
These bits determine the ADC range as indicated below:
1.25 V11
2.5 V01
5 V10
10 V00
RangeGS0GS1
SEDIFF
Selects measurement configuration for the Analog Front-End.
1 = Analog Front-End in Single-Ended Mode. This mode supports up to 16 channels.
0 = Analog Front-End in Differential Mode. This mode supports up to 8 channels.
UNIBIP
Selects offset configuration for the Analog Front End.
1 = Analog Front-End Unipolar for selected range
0 = Analog Front-End Bipolar for selected range.
The following table summarizes all possible Offset/Range configurations:
22