PCI-DAS1602/12 PCI Bus Data Acquisition Board User’s Manual Revision 4, September 2001 ME A S U R E M E NT CO MP U T I N G CO RP O RA T I O N
LIFETIME WARRANTY Every hardware product manufactured by Measurement Computing Corp. is warranted against defects in materials or workmanship for the life of the product, to the original purchaser. Any products found to be defective will be repaired or replaced promptly. LIFETIME HARSH ENVIRONMENT WARRANTYTM Any Measurement Computing Corp. product which is damaged due to misuse may be replaced for only 50% of the current price.
Table of Contents . . . . . . . . . . . . . ................................................ 1 1.0 INTRODUCTION 1.1 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.2 Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1.0 INTRODUCTION 1.1 FUNCTIONAL DESCRIPTION The PCI-DAS1602/12 multifunction analog and digital I/O board sets a new standard for high performance data acquisition on the PCI bus. It can sample analog inputs at rates up to 330 kHz. The board provides 16, single-ended, or 8, differential, 12-bit analog inputs, 24 bits of digital I/O, three, 16-bit down-counters. The PCI-DAS1602/12 has an analog trigger input with trigger levels and direction selectable by software.
1.1.3 Analog Outputs The PCI-DAS1602/12 provides two channels of high-speed 12-bit analog output. The analog outputs are updated via an on-board FIFO and REP OUTSW commands and provide a 250 kHz maximum update rate. Software selectable output ranges of 0 to 10V, 0 to 5V, ±10V and ±5V are provided, and channels may be set at different ranges. The D/A outputs provide rated accuracy to ±5 mA, are short circuit protected (25 mA limit) and are cleared to 0 volts on power up or reset. 1.1.
2.0 INSTALLATION 2.1 SOFTWARE INSTALLATION In order to easily test your installation, it is recommended that you install InstaCal the installation, calibration and test utility that was supplied with your board. Refer to the Software Installation Manual for information on the initial setup, loading, and installation of InstaCal (and optional Universal Library software if purchased). 2.2 HARDWARE INSTALLATION The PCI-DAS1602-12 is completely plug and play. There are no switches or jumpers to set.
Analog Ground Analog Input Ch 0 High Analog Input Ch 0 Low / 8 High Analog Input Ch 1 High Analog Input Ch 1 Low / 9 High Analog Input Ch 2 High Analog Input Ch 2 Low / 10 High Analog Input Ch 3 High Analog Input Ch 3 Low / 11 High Analog Input Ch 4 High Analog Input Ch 4 Low / 12 High Analog Input Ch 5 High Analog Input Ch 5 Low / 13 High Analog Input Ch 6High Analog Input Ch 6 Low / 14 High Analog Input Ch 7 High Analog Input Ch 7 Low / 15 High Analog Ground NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
C100FF-XX CABLE PCI-DAS1602/12 100-Pin Connector ANALOG I/O PINS 1 TO 50 ANALOG SIGNAL CONDITIONING or CIO-MINI50 DIGITAL I/O PINS 51 TO 100 CIO-MINI50 or DIGITAL SIGNAL CONDITIONING Figure 3-2.
Figure 3-3.
4.0 ANALOG CONNECTIONS 4.1 ANALOG INPUTS Analog signal connection is one of the most challenging aspects of applying a data acquisition board. If you are an Analog Electrical Engineer, this section is not for you, but if you are like most PC data acquisition users, the best way to connect your analog inputs may not be obvious.
C H IN ~ + In pu t Am p V s + Vg2 - V g1 Vs LL G N D To A /D - g2 g1 A ny volta ge differe ntial betwee n groun ds g1 and g2 sh ows up a s an error signal at the inp ut a m plifier S ingle -en ded inp ut w ith C o m m o n M ode Voltag e Differential Inputs Differential inputs measure the voltage between two distinct input signals. Within a certain range (referred to as the common mode range), the measurement is almost independent of signal source to PCI-DAS1602/12 ground variations.
Before moving on to the discussion of grounding and isolation, it is important to explain the concepts of common mode, and common mode range (CM Range). Common mode voltage is depicted in the diagram above as Vcm. Though differential inputs measure the voltage between two signals, without (almost) respect to the either signal’s voltages relative to ground, there is a limit to how far away from ground either signal can go.
Which system do you have? Try the following experiment. Using a battery powered voltmeter*, measure the voltage (difference) between the ground signal at your signal source and at your PC. Place one voltmeter probe on the PC ground and the other on the signal source ground. Measure both the ac and dc voltages. *If you do not have access to a voltmeter, skip this experiment and take a look a the following three sections. You may be able to identify your system type from the descriptions provided.
The most frequently encountered grounding scenario involves grounds that are somehow connected, but have ac and/or dc offset voltages between the PCI-DAS1602/12 and signal source grounds. This offset voltage my be ac, dc, or both and may be caused by a wide array of phenomena including EMI pickup, resistive voltage drops in ground wiring and connections, etc.
4.2 WIRING CONFIGURATIONS Combining all the grounding and input type possibilities provides us with the following potential connection configurations. The combinations along with our recommendations on usage are shown in the chart below.
l S ig n a rc e w it h d S ou on Gn Comm C H IN LL G N D O p tio na l w ire since sig na l s ou rce an d A /D bo ard sh are co m m on g rou nd + Inp ut Amp To A /D - I/O C o nn e c to r A /D B o a rd S ig n a l s o u rc e a n d A /D b o a rd s h a rin g c o m m o n g ro u n d c o n n e c te d to s in g le -e n d e d in p u t. 4.2.
S ig n a e l S o u rc o m m o n w it h C d e V o lt a g e Mo GND C H H igh + Inp u t Amp To A /D - C H L ow LL G N D T he v oltag e diffe ren tia l be tw een the se gro un ds , ad de d to the m a xim u m in pu t s ig nal m us t s tay w ithin + /-10V I/O C o n n e cto r A /D B o a rd S ig n a l s o urc e a n d A /D b o a rd w ith c o m m o n m o d e v o lta g e c o n n e c te d to a d iffe re n tia l in p u t. 4.2.
4.2.6 Isolated Grounds / Single-Ended Inputs Single-ended inputs can be used to monitor isolated inputs, though the use of the differential mode will increase your system’s noise immunity. The diagram below shows the recommended connections in this configuration. d Is o la te ig n a l s e so u rc C H IN + In p u t Amp To A /D - LL G N D I/O C o n n e c to r A /D B o a rd Isolated Signal Source C onne cted to a Single-Ended Input 4.2.
5.0 PROGRAMMING & APPLICATIONS Your PCI-DAS1602/12 is supported by Measurement Computing’s powerful Universal Library. We strongly recommend that you take advantage of the Universal Library as your software interface. The complexity of the registers required for automatic calibration combined with the dynamic allocation of addresses and internal resources makes the PCI-DAS1602/12 series very challenging to program via direct register I/O operations.
6.0 SELF-CALIBRATION The PCI-DAS1602/12 is shipped fully-calibrated from the factory with calibration coefficients stored in nvRAM. At run time, these calibration factors can be loaded into system memory and can be automatically retrieved each time a different DAC/ADC range is specified. The user has the option to recalibrate with respect to the factory-measured voltage standards at any time by simply selecting the “Calibrate” option in InstaCal.
The calibration scheme for the Analog Out section is shown in Figure 6-2 below. This circuit is duplcated for both DAC0 and DAC1 12 R ef T rim D ac (coarse) T rim D ac (fine) DAC A n alog O u t G a in A d j. O ffse t A d j. T rim D ac Figure 6-2.
7.0 REGISTER DESCRIPTION 7.1 REGISTER OVERVIEW PCI-DAS1602/12 operation registers are mapped into I/O address space. Unlike ISA bus designs, this board has several base addresses, each corresponding to a reserved block of addresses in I/O space. As we mention in our programming chapter, we highly recommend customers use the Universal Library package. Direct register level programming should be attempted only by extremely experienced register level programmers.
WRITE 15 14 13 12 - DAEMCL ADFLCL DAEMIE 11 10 9 8 7 - - - - INTCL 6 5 EOACL DAHFCL 4 EOAIE 3 2 1 DAHFIE INTE INT1 0 INT0 Write operations to this register allow the user to select interrupt sources, enable interrupts, clear interrupts as well as ADC FIFO flags. The following is a description of the Interrupt/ADC FIFO Register: INT[1:0] General Interrupt Source selection bits.
DAEMCL A write-clear to reset DAEM interrupt status. 1= Clear DAEM interrupt. 0 = No effect. NOTE: It is not necessary to reset any write-clear bits after they are set. READ 15 - 14 13 DAEMI LADFUL 12 11 10 9 8 7 6 5 4 3 2 1 0 ADNE ADNEI ADHFI EOBI XINTI INT EOAI DAHFI - - - - - Read operations on this register allow the user to check status of the selected interrupts and ADC FIFO flags.
0 = Indicates non-overflow condition of ADC FIFO. Status bit of DAC FIFO Empty interrupt. Used to indicate that a FIFO'd DAC operation has completed. 1 = DAC FIFO Empty interrupt condition has occurred. 0 = DAC FIFO Empty interrupt condition has not occurred. DAEMI 7.3.2 ADC CHANNEL MUX AND CONTROL REGISTER BADR1 + 2 This register sets channel MUX HI/LO limits, ADC gain, offset and pacer source. A Read/Write register.
UNIBIP GS1 GS0 Input Range Input Gain Measurement Resolution 0 0 0 ±10 V 1 4.88 mV 0 0 1 ±5V 2 2.44 mV 0 1 0 ±2.5 V 4 1.22 mV 0 1 1 ±1.25 V 8 610 µV 1 0 0 0 to10 V 1 2.44 mV 1 0 1 0 to 5 V 2 1.22 mV 1 1 0 0 to 2.5 V 4 610 µV 1 1 1 0 to 1.25 V 8 305 µV ADPS[1:0] These bits select the ADC Pacer Source. Maximum Internal/External Pacer frequency is 330 kHz.
TS[1:0] These bits select one-of-three possible ADC Trigger Sources: TS1 TS0 Source 0 0 Disabled 0 1 Software Trigger 1 0 External (Digital) 1 1 External (Analog) Note: TS[1:0] should be set to 0 while setting up Pacer source and count values. This bit sets the polarity for the external trigger/gate. Internally, the ADC is triggered on TGPOL a rising edge or gated on with an active high signal. Use TGPOL to condition external trigger/gate for proper polarity.
0 = No Effect. These bits select the Analog Trigger/Gate Mode as described in the table below. Note that the CHI Threshold is set by DAC1, CLO Threshold is set by DAC0. CHI >= CLO by definition. HI_EN, CLO_EN, HMODE CHI_EN CLO_EN HMODE Analog Trigger/Gate Function Mode 0 0 0 Signal goes HIGH when ATRIG is more positive than CHI. Signal goes low when ATRIG becomes more negative than CLO. Hysteresis level is the difference between CHI and CLO.
This bit allows the user to select the clock source for user Counter 0. 1 = Internal 10 MHz oscillator 0 = External clock source input via CTR0CLK pin on 100-pin connector. C0SRC READ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - INDX_GT - - - - XTRIG - - - - - - - XTRIG 1 = External Trigger flip-flop has been set. This bit is write-cleared. 0 = External Trigger flip-flop reset. No trigger has been received. INDX_GT 1 = Pre-trigger index counter has completed its count.
CSRC[2:0] These bits select the different calibration sources available to the ADC front end. CSRC2 CSRC1 CSRC0 Cal Source 0 0 0 AGND 0 0 1 7.0V 0 1 0 3.5V 0 1 1 1.75V 1 0 0 0.875V 1 0 1 8.6mV 1 1 0 VDAC0 1 1 1 VDAC1 CALEN This bit is used to enable Cal Mode. 1 = Selected Cal Source, CSRC[2:0], is fed into Analog Channel 0. 0 = Analog Channel 0 functions as normal input. SDI Serial Data In.
DAPS[1:0] These bits select the DAC Pacer Source: DAPS1 DAPS0 Pacer Source 0 0 SW Convert 0 1 Internal 82C54 Programmed via BADR3 + 9, + A 1 0 External Falling Edge 1 1 External Rising Edge These bits select the High-Speed DAC Modes as follows: HS[1:0] DACnR[1:0] HS1 HS0 DAC Mode 0 0 Disabled 0 1 DAC0 1 0 DAC1 1 1 Simultaneous DAC0/1 These bits select the independent gains/ranges for either DAC0 or DAC1. n=0 for DAC0 and n=1 for DAC1.
7.4 BADR2 The I/O Region defined by BADR2 contains the ADC Data register and the ADC FIFO clear register. 7.4.1 ADC DATA REGISTER BADR2 + 0 ADC Data register. WRITE Writing to this register is only valid for software-initiated conversions. The ADC Pacer source must be set to 00 via the ADPS[1:0] bits. A null write to BADR2 + 0 with begin a single conversion. Conversion status may be determined in two ways.
7.5 BADR3 The I/O Region defined by BADR3 contains data and control registers for the ADC Pacer, DAC Pacer, Pre/Post-Trigger Counters and Digital I/O bytes. The PCI-DAS1602/12 has two 8254 counter/timer devices.
8254A COUNTER 2 DATA - ADC PACER DIVIDER UPPER BASE + 2 READ/WRITE 7 D7 6 5 4 2 3 1 0 D6 D5 D4 D3 D2 D1 D0 Counter 1 provides the lower 16 bits of the 32-bit pacer clock divider. Its output is tied to the clock input of Counter 2 which provides the upper 16-bits of the pacer clock divider. The clock input to Counter 1 is a precision 10 MHz oscillator source. Counter 2 output is called the 'Internal Pacer' and can be selected by software to be the ADC Pacer source.
7 6 5 4 2 3 1 0 D7 D6 D5 D4 D3 D2 D1 D0 DIO PORT B DATA BADR3 + 5 PORT B can be configured as an 8-bit input or output channel. Functionality is the same as PORT A. READ/WRITE 7 6 5 4 2 3 1 0 D7 D6 D5 D4 D3 D2 D1 D0 DIO PORT C DATA BADR3 + 6 PORT C can be configured as an 8-bit port of either inputs or outputs, or it can be split into two independent 4-bit ports for inputs or outputs.
D4 D3 D1 D0 PORT A PORT C UPPER PORT B PORT C LOWER HEX DECIMAL 0 0 0 0 OUT OUT OUT OUT 80 128 0 0 0 1 OUT OUT OUT IN 81 129 0 0 1 0 OUT OUT IN OUT 82 130 0 0 1 1 OUT OUT IN IN 83 131 0 1 0 0 OUT IN OUT OUT 88 136 0 1 0 1 OUT IN OUT IN 89 137 0 1 1 0 OUT IN IN OUT 8A 138 0 1 1 1 OUT IN IN IN 8B 139 1 0 0 0 IN OUT OUT OUT 90 144 1 0 0 1 IN OUT OUT IN 91 145 1 0 1 0 IN OUT IN OUT 92 146 1 0
8254B COUNTER 1 DATA - DAC PACER DIVIDER LOWER BADR3 + 9 READ/WRITE 7 D7 6 5 4 2 3 1 0 D6 D5 D4 D3 D2 D1 D0 8254B COUNTER 2 DATA - DAC PACER DIVIDER UPPER BADR3 + Ah READ/WRITE 7 D7 6 5 4 2 3 1 0 D6 D5 D4 D3 D2 D1 D0 Counter 1 provides the lower 16 bits of the 32-bit pacer clock divider. Its output is fed to the clock input of Counter 2 which provides the upper 16-bits of the pacer clock divider. The clock input to Counter 1 is a precision 10 MHz oscillator source.
7.6.1 DAC DATA REGISTER BADR4 + 0 DAC Data register. A Write-only register. WRITE 15 14 13 12 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 MSB LSB These bits represent the DAC data word.
7.6.2 DAC FIFO CLEAR REGISTER BADR4 + 2 The DAC FIFO Clear register is a write-only register. A write to this address location clears the DAC FIFO. Data is don't care. Clear the DAC FIFO before all new DAC operations. .
8.0 SPECIFICATIONS Typical for 25°C unless otherwise specified. POWER CONSUMPTION +5V +12V Table 1. Power Consumption 1.2A typical, 1.5A max 30 mA maximum ANALOG INPUT SECTION A/D converter type Resolution Number of channels Input ranges (SW programmable) Polarity A/D pacing (SW programmable) Burst mode A/D Triggering Modes A/D trigger sources Data transfer A/D conversion time Throughput Calibration Table 2.
ACCURACY – ANALOG INPUTS 330 kHz sampling rate, single channel operation and a 60-minute warm-up: Accuracies are listed for operational temperatures within ±2°C of internal calibration temperature. Calibrator test source high side tied to Channel 0 High and low side tied to Channel 0 Low. Low-level ground is tied to Channel 0 Low at the user connector. Table 3 – Absolute Accuracy – Analog Inputs Range ±10.000V ±5.000V ±2.500V ±1.250V 0V to +10.000V 0V to +5.000V 0V to +2.500V 0V to +1.250V Range ±10.
Noise Performance Table 6 below summarizes the noise performance for the PCI-DAS1602/12. Noise distribution is determined by gathering 50K samples @ 330 kHz with inputs tied to ground at the user connector. Table 6 – Board Noise Performance % within ±2 % within ±1 MaxCounts counts count ±10.00V 100% 100% 3 ±5.000V 100% 100% 3 ±2.500V 100% 100% 3 ±1.250V 100% 100% 5 0 to +10.00V 100% 100% 3 0 to +5.000V 100% 100% 3 0 to +2.500V 100% 100% 3 0 to +1.
Range ±10.00V ±5.000V 0 to +10.00V 0 to +5.000V Table 9 – Accuracy Components (errors in LSBs) Gain Error (LSB) Offset Error (LSB) DLE (LSB) ±2.0 max ±0.1 max ±1.0 max ±2.0 max ±0.2 max ±1.0 max ±2.0 max ±0.2 max ±1.0 max ±2.0 max ±0.4 max ±1.0 max ILE (LSB) ±1.0 max ±1.0 max ±1.0 max ±1.0 max Each PCI-DAS1602/12 is tested at the factory to assure the board’s overall error does not exceed ±3.0 LSB. Total board error is a combination of Gain, Offset, Integral Linearity and Differential Linearity error.
INTERRUPTS Interrupt PCI Interrupt enable Interrupt sources Table 12.
Counter 6 – DAC pacer upper divider Counter 6 Source Counter 6 Gate Counter 6 Output Gate width high Gate width low Input High Input Low Output High Output Low Crystal Oscillator Frequency Counter 5 output Tied to Counter 5 gate, programmable source. DAC Pacer clock, available at user connector (D/A Internal Pacer Output) 50 ns min 50 ns min 2.0 volts min, 5.5 volts absolute max 0.8 volts max, −0.5 volts absolute min 3.0 volts min @ −2.5mA 0.4 volts max @ 2.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Table 18.
Table 19.
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