Specifications

HOST SOFTWARE INTERFACE
6 – 39
Reset and Interrupt Handling
Reset Handling
One of three different conditions may cause a reset: power on, hardware reset or software reset. All three cause the
interface processor to initialize itself and the Task File registers of the interface. A reset also causes a set of the Busy bit in the
Status register. The Busy bit does not clear until the reset clears and the drive completes initialization. Completion of a
reset operation does not generate a host interrupt.
Task File registers are initialized as follows:
Error 1
Sector Count 1
Sector Number 1
Cylinder Low 0
Cylinder High 0
Drive/Head 0
Interrupt Handling
The drive requests data transfers to and from the host by asserting its IRQ 14 signal. This signal interrupts the host if
enabled by bit 1 (IRQ enable) of the Fixed Disk Control register.
Clear this interrupt by reading the Status register, writing the Command register, or by executing a host hardware or
software reset.