Specifications

LEON-G100/G200 - System Integration Manual
GSM.G1-HW-09002-C Preliminary System description
Page 46 of 75
V
Fig. 30: UART interface application circuit with complete V.24 link in the DTE/DCE serial communication
Using TxD, RxD, RTS and CTS lines (not using the complete V.24 link)
Follow the application circuit described in Figure 31. In this case the HW flow-control is used. The module wakes
up from default idle-mode to active-mode when data is received at the UART interface, since the HW flow
control is enabled by default in the module. In the application circuit a loop from the module DSR output line to
the module DTR input line must be implemented because the module needs DTR active (low electrical level) and
DSR is active (low electrical level) once the module is switched on and the UART interface is enabled. The DCD
and RI lines of the module can be left unconnected and floating.
Figure 31: UART interface application circuit with partial V.24 link (4-wire) in the DTE/DCE serial communication
Using only TxD and RxD lines (not complete V24 link)
Follow the application circuit described in the Figure 32. In this case the HW flow control is not used. The
module doesn’t wake up from the default idle-mode to active-mode when data is received at the UART
interface. Since the HW flow control is by default enabled in the module, data delivered by the DTE can be lost.
In the application circuit a loop from the module CTS output line to the module RTS input line is provided
LEON-G100/G200
(DCE)
Application Processor
(DTE)
15
16
TxD
RxD
13
14
RTS
CTS
11
10
9
12
DTR
DSR
RI
DCD
TxD
RxD
RTS
CTS
DTR
DSR
RI
DCD
LEON-G100/G200
(DCE)
Application Processor
(DTE)
15
16
TxD
RxD
13
14
RTS
CTS
11
10
9
12
DTR
DSR
RI
DCD
TxD
RxD
RTS
CTS
DTR
DSR
RI
DCD
LEON-G100/G200
(DCE)
Application Processor
(DTE)
15
16
TxD
RxD
13
14
RTS
CTS
11
10
9
12
DTR
DSR
RI
DCD
TxD
RxD
RTS
CTS
DTR
DSR
RI
DCD
LEON-G100/G200
(DCE)
Application Processor
(DTE)
15
16
TxD
RxD
13
14
RTS
CTS
11
10
9
12
DTR
DSR
RI
DCD
TxD
RxD
RTS
CTS
DTR
DSR
RI
DCD