Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 33
The signals that need special consideration are: SATA_T[0:3]n, SATA_T[0:3]p, SATA_R[0:3]n, SATA_R[0:3]p,
SATA_DET#[0:3], SATA_PWREN#[0:3], LPC_CLK, LPC_AD[0:3], LPC_FRAME#, LPC_SERIRQ#, LPC_DRQ#.
• The CPU SHALL NOT DRIVE these signals until it determines that there is not a Bus Stacking Error.
• If the system detects a bus stacking error, it must remain in reset and not drive these signals.
• The CPU must tolerate PCI Express signal levels on these signals during reset.
The rules for all host CPUs are detailed below and affect the operation of pins 52, 54, and 105 on PCIe/104 Connector A.
Table 4-4 Host CPU Stacking Rules
Host 53 STK0/WAKE# 54 STK1/PEG_ENA# 105 STK2/SDVO_DAT
Type 1
During Reset:
0 = Bus Stacking Error
1 = Normal Operation
0 = Enable PCIe x16
1 = Enable GFX(optional)
0 = Enable PCIe x16
1 = Enable GFX(optional)
Type 2
0 = Normal Operation
1 = Normal Operation
0 = Bus Stacking Error
1 = Normal Operation
0 = Normal Operation
1 = Bus Stacking Error
Table 4-5 Required Host Connector A Pin Configuration
Host Type
53 STK0/WAKE# 54 STK1/PEG_ENA# 105 STK2/SDVO_DAT
Type 1
Input (100K Pull-up) Input (100K Pull-up) Input (100K Pull-down)
Type 2
Input (100K Pull-up) Input (1K Pull-up): Input (100K Pull-down):
• All pull-ups described above must be to 3.3V that is derived from the +5V_Always supply. If a board does not
have the appropriate supply, a Thevenin equivalent resistor divider may be used. All pull-downs are to ground.
4.3. Peripheral Configuration Rules
The signals that need special consideration are: SATA_T[0:3]n, SATA_T[0:3]p, SATA_R[0:3]n, SATA_R[0:3]p,
SATA_DET#[0:3], SATA_PWREN#[0:3], LPC_CLK, LPC_AD[0:3], LPC_FRAME#, LPC_SERIRQ#, LPC_DRQ#.
• Peripheral cards MUST NOT DRIVE these signals while PE_RST# is asserted.
• The peripheral cards must tolerate PCI Express signal levels on these signals during reset.
Rules guiding peripheral boards are listed in Table 4-6.
Table 4-6 Peripheral Stacking Rules
Bus
Peripheral Interface 53 - STK0/WAKE# 54 – STK1/PEG_ENA# 105 – STK2/SDVO_DAT
Type 1 PCIe x16 or x8 Hi-Z During Reset Short to GND Open
Type 1 Alternate Function Open Open 1K to 10K Pull-up
Type 2 SATA, USB 3.0, LPC Short to GND Open Open
Universal PCIe x4 Hi-Z During Reset 10K Pull-down Open
Universal PCIe x1 or USB 2.0 Hi-Z During Reset Open Open
• All pull-ups described above must be to 3.3V that is derived from the +5V_Always supply. If a board does not
have the appropriate supply, a Thevenin equivalent resistor divider may be used.
• A peripheral device must be able to be stacked above or below the Host. Therefore, the peripheral must be
capable of selecting the TX, RX, and clock lines from the top connector or the bottom connector.
• If any link(s) from a Link group (PCI Express x1, PCI Express x4, PCI Express x8, USB 2.0, USB 3.0, or
SATA) is used on the module, the other links in that group must be shifted to the appropriate positions.
• Any unused signals must be passed between top and bottom using no more than two vias and as short of a trace
as possible.