Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 29
3.3. Signal Descriptions
Table 3-1 Connector B Signals
Table 3-1 shows only the required pins, arranged in functional groups, which are required for the stackable PCI
Expansion bus. This version of the PCI bus is intended as a 32-bit bus running at 33MHz as defined in the PCI Local
Bus Specification Revision 2.2, and therefore, 64-bit extension and 66MHz
1
are not supported at this time. Also not
supported are the boundary scan features (JTAG), Present (PRSNT [1:2]#), and Clock running (CLKRUN#). The
direction indication on the pins assumes a combination master/target device.
1
The PCI bus has been simulated at 33MHz. For the purpose of this specification, 66MHz is not supported. To support
future enhancements, the M66EN signal should be grounded on any module that cannot support 66MHz and left open for
modules that can support a 66MHz clock.
# Pins Signal Name Group Description
32 AD[31:00]
PCI Bus
Address and Data are multiplexed on the same PCI pins. A bus transaction
consists of an address phase followed by one or more data phases.
4 C/BE[0,3]#
Bus Command/Byte Enables are multiplexed. During the address phase of
a transaction, they define the bus command. During the data phase, they are
used as byte enables.
1 PAR
Parity is even parity across AD [31:00] and C/BE [3:0]#. Parity generation
is required by all PCI signals.
1 FRAME#
Cycle Frame is driven by the current master to indicate the beginning of an
access and will remain active until the final data cycle.
1 TRDY#
Target Ready indicates the selected device’s ability to complete the current
data phase of the transaction. Both IRDY# and TRDY# must be asserted to
terminate a data cycle.
1 IRDY#
Initiator Ready indicates the bus master's ability to complete the current
data phase of the transaction.
1 STOP#
Stop indicates the current selected device is requesting the master to stop the
current transaction.
1 DEVSEL#
Device Select, when actively driven, indicates the driving device has
decoded its address as the target of the current access.
4 IDSEL[0,3]
Initialization Device Select is used as a chip-select during configuration
read and write transactions.
1 LOCK#
Lock indicates an atomic operation to a bridge that may require multiple
transactions to complete.
1 PERR# Parity Error is for reporting data parity errors.
1 SERR# System Error is for reporting address parity errors.
4 REQ#[0,3] Request indicates to the arbitrator that this device desires use of the bus.
4 GNT#[0,3] Grant indicates to the requesting device that access has been granted.
4 CLK[0,3]
Clock provides timing for all transactions on the PCI bus and is an input to
every PCI device.
1 RST#
Reset is used to bring PCI-specific registers, sequencers, and signals to a
consistent state.
1 M66EN
66 MHz Enable indicates to a device whether the bus segment is operating
at 33 MHz or 66 MHz. The PCI bus has been simulated at 33MHz. For the
purpose of this specification, 66MHz is not supported.
1 INTA# Interrupt A is used to request Interrupts.
1 INTB# Interrupt B is used to request Interrupts.
1 INTC# Interrupt C is used to request Interrupts.
1 INTD# Interrupt D is used to request Interrupts.
1 PME#
ATX
Power
Supply
Power Management Event such as wake-on-LAN
1 +5V_SB
Standby Power for advanced power saving modes. Always on
1 PSON# Power Supply On brings the ATX power supply out of sleep mode.
5 VI/O
Power
10 +3.3V +3.3V power lines
8 +5V +5V power lines
1 +12V +12V power line
1 -12V -12V power line
25 GND Ground lines