Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 23
2.8. Routing Topology
2.8.1 PCI Express and USB 3.0
Figure 2-6 below shows the positioning of the DC blocking capacitor and PCIe/104 connector in relation to the Host and
Device. The DC blocking capacitor is placed on the transmit signals. This will be the signals the Host drives onto the Tx
bus connector’s pins and the signals the Device drives onto the Rx signals of the connector. The actual position is not
critical; however the position must be closely matched between the signals of a differential pair.
Figure 2-6 PCI Express and USB 3.0 Capacitor Placement
Table 2-10 below list the general guide lines for PCI Express routing.
Table 2-10 PCI Express and USB 3.0 Routing Specification
Interface
Differential
Impedance
(Ohm)
Matching
in a pair
mil (mm)
Matching
pair to pair
mil (mm)
PCIe Gen 1, 2 & 3 Capable 85 ±15% 5 (0.13) Not required
PCIe Gen 1 only 100 ±20% 5 (0.13) Not required
PCIe Pass Through 85 ±15% 5 (0.13) Not required
USB 3.0 96 ±15% N/A N/A