Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 22
2.7. Layout Recommendations
The Data rate for PCI Express Generation 1 is 2.5 Gbps, Generation 2 is 5.0 Gbps, and Generation 3 is 8.0 Gbps. This
means that significant frequency content exists up to 1.25 GHz for Generation 1, 2.50 GHz for Generation 2, and 4.0GHz
for Generation 3. At these speeds, PCB layout becomes very critical. Therefore, the following recommendations should
be followed to avoid signal integrity problems:
• Route all PCI Express signal lines (Transmit and Receive) as controlled impedance using microstrip, stripline,
or similar techniques.
o 68 – 105 differential pairs, 85 recommended.
• Spacing from a link to its neighbor must be at least 20 mils (0.51 mm) in the main routing region, 15 mils (0.38
mm) for stripline breakout, and 12 mils (0.30 mm) for microstrip breakout.
• Symmetrical routing must be used between the two signals of a differential pair.
• Signals in a differential pair must be matched to within 5 mils (0.13 mm).
• AC coupling capacitors must be provided on the TX lines. Values should be between 75nF and 200nF. A
surface mount capacitor must be used.
• All PCI Express signals should be routed in an adjacent layer to a ground plane.
• There shall be no stubs except the short stub caused by the unused end of the Host connector. SI testing has
shown this very short stub to be insignificant in a system with a Host and 6 add-in cards. No stubs are
recommended on the Host at Gen 2.
• Do not use 90 degree bends. Use 45 degree bends or curves.
Table 2-9: Via and Trace Length Budget
Location Max. Vias Max. Trace Length mil (mm) Notes
Host TX lines Gen 1 & 2 4 6000 (152.40) Both sides of AC capacitor
Host TX lines Gen 3 4 4000 (101.60) Both sides of AC capacitor
Host RX lines Gen 1 & 2 2 6000 (152.40)
Host RX lines Gen 3 2 4000 (101.60)
Device TX Lines 4 4000 (101.60) Both sides of signal switch.
Device RX lines 4 4000 (101.60) Both sides of signal switch.
Pass-through (lane shifting) 2 1000 (25.40) Includes stack height
2.7.1 Stitching Capacitors
Bypass these pins with a 0.01uF capacitor to ground as close as possible to the pin. This will ensure a good return
path to ground for all clock signals.
• Pin 39, 5V_SB
• Pin 40, 5V_SB
• Pin 45, DIR
• Pin 46, PWRGOOD
• Pin 52, PSON#
2.7.2 Number of PCI Express Boards in the Stack
The last PCI Express Generation 1, SATA 1 or SATA 2 peripheral in a stack shall have no more than 10 boards between
it and the host. The last PCI Express Generation 2 or USB 3.0 peripheral in a stack shall have no more than 9 boards
between it and the host. The last PCI Express Generation 3 or SATA 3 peripheral in a stack shall have no more than 5
boards between it and the host.