Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 21
2.5. Switching
To ensure that all Device modules can be stacked up or down without manual configuration a signal switch is required on
the Device. The switch is only required on interface being used. For example a SATA Device will have a switch on the
SATA link, but will not have switches on USB 3.0 or PCI Express links.
2.5.1 Signal Switch
A signal switch is an analog multiplexer that can be used to select between the link on top connector or the bottom
connector. This switch must be able to perform well at the high data rates found in the PCI Express, SATA, or USB 3.0
signaling environment.
Several initial candidates for signal switches have been identified and listed in Table 2-8. These switches have advertised
specifications that meet the requirements of the application but have not been independently verified. Equivalent
substitutes are permitted.
Table 2-8: Signal Switches or equivalent
Manufacturer Part Number Application
Texas Instruments TS2PCIE2212 PCIe 1
Pericom PI2PCIE2442 PCIe 1
Texas Instruments DS25MB100 PCIe 1
NXP CBTU0808EE/G PCIe 1
Pericom PI2PCIE2442 PCIe 2
Maxim MAX4889A PCIe 2
Pericom PI3PCIE3412 PCIe 3
Pericom PI2USB3212 USB 3.0
Pericom PI2DBS212 SATA 3
NXP CBTU04083 PCIe 3, SATA 6 or USB 3.0
2.6. System Clocking
The PCI Express architecture is based on a 100 MHz reference clock that is distributed from the Host to the Devices.
The Host may employ spread spectrum clocking as defined in the PCI Express Base Specification to reduce EMI. For
this reason it is recommended that Devices always use the distributed clock as its reference clock. Using an on-board
oscillator as a reference is not allowed.
PCIe/104 does not provide for any termination on unused clock lines, therefore the Host is required to disable any unused
clocks.
Because there is only one clock provided for the Type 1 PCI Express x16 Link or the Type 2 PCI Express x4 links and
potentially two devices, any Device that operates at x8 or x4 must re-drive the clock. The clock must not incur more than
10ns of phase delay when it is re-driven.