Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 15
Table 2-6: x16 Link as Two x8 or Two x4 Links Top Connector
Host Transmit Signals Host Receive Signals
x16 Signal x8 Signal x4 Signal x16 Signal x8 Signal x4 Signal
PEx16_0T(5) PEx8_0T(5) PEx16_0R(5) PEx8_0R(5)
PEx16_0T(6) PEx8_0T(6) PEx16_0R(6) PEx8_0R(6)
PEx16_0T(7) PEx8_0T(7) PEx16_0R(7) PEx8_0R(7)
PEx16_0T(8) PEx8_1T(0) PEx4_1T(0) PEx16_0R(8) PEx8_1R(0) PEx4_1R(0)
PEx16_0T(9) PEx8_1T(1) PEx4_1T(1) PEx16_0R(9) PEx8_1R(1) PEx4_1R(1)
PEx16_0T(10) PEx8_1T(2) PEx4_1T(2) PEx16_0R(10) PEx8_1R(2) PEx4_1R(2)
PEx16_0T(11) PEx8_1T(3) PEx4_1T(3) PEx16_0R(11) PEx8_1R(3) PEx4_1R(3)
PEx16_0T(12) PEx8_1T(4) PEx16_0R(12) PEx8_1R(4)
PEx16_0T(13) PEx8_1T(5) PEx16_0R(13) PEx8_1R(5)
PEx16_0T(14) PEx8_1T(6) PEx16_0R(14) PEx8_1R(6)
PEx16_0T(15) PEx8_1T(7) PEx16_0R(15) PEx8_1R(7)
Table 2-7: x16 Link as Two x8 or Two x4 Links Bottom Connector
Host Transmit Signals Host Receive Signals
x16 Signal x8 Signal x4 Signal x16 Signal x8 Signal x4 Signal
PEx16_0T(0) PEx8_1T(0) PEx4_1T(0) PEx16_0R(0) PEx8_1R(0) PEx4_1R(0)
PEx16_0T(1) PEx8_1T(1) PEx4_1T(1) PEx16_0R(1) PEx8_1R(1) PEx4_1R(1)
PEx16_0T(2) PEx8_1T(2) PEx4_1T(2) PEx16_0R(2) PEx8_1R(2) PEx4_1R(2)
PEx16_0T(3) PEx8_1T(3) PEx4_1T(3) PEx16_0R(3) PEx8_1R(3) PEx4_1R(3)
PEx16_0T(4) PEx8_1T(4) PEx16_0R(4) PEx8_1R(4)
PEx16_0T(5) PEx8_1T(5) PEx16_0R(5) PEx8_1R(5)
PEx16_0T(6) PEx8_1T(6) PEx16_0R(6) PEx8_1R(6)
PEx16_0T(7) PEx8_1T(7) PEx16_0R(7) PEx8_1R(7)
PEx16_0T(8) PEx8_0T(0) PEx4_0T(0) PEx16_0R(8) PEx8_0R(0) PEx4_0R(0)
PEx16_0T(9) PEx8_0T(1) PEx4_0T(1) PEx16_0R(9) PEx8_0R(1) PEx4_0R(1)
PEx16_0T(10) PEx8_0T(2) PEx4_0T(2) PEx16_0R(10) PEx8_0R(2) PEx4_0R(2)
PEx16_0T(11) PEx8_0T(3) PEx4_0T(3) PEx16_0R(11) PEx8_0R(3) PEx4_0R(3)
PEx16_0T(12) PEx8_0T(4) PEx16_0R(12) PEx8_0R(4)
PEx16_0T(13) PEx8_0T(5) PEx16_0R(13) PEx8_0R(5)
PEx16_0T(14) PEx8_0T(6) PEx16_0R(14) PEx8_0R(6)
PEx16_0T(15) PEx8_0T(7) PEx16_0R(15) PEx8_0R(7)
2.4.2 PEG_ENA# Signal
The PEG_ENA# signal is used to indicate the presence of a device on the x16 Link. This signal is pulled up at the Host.
Any Device that uses the x16 Link (or the x16 as an x8 or x4) attaches this signal to ground. When the Host sees this
signal high, indicating that an x16 Device is not present, it may disable the x16 Link, or convert it to alternate uses, such
as Alternate Functions as defined by the CPU/chipset.
2.4.3 DIR Signal
The DIR line provides a means for the Devices to select the correct PCI Express, SATA, or USB Link depending if it is
above or below the Host in the stack.