Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 14
Table 2-5 Connector A, OneBank Pin Assignments
1 USB_OC# PE_RST# 2 2 PE_RST# USB_OC# 1
3
3.3V 3.3V
44
3.3V 3.3V
3
5 USB_1p USB_0p 6 6 USB_0p USB_1p 5
7 USB_1n USB_0n 8 8 USB_0n USB_1n 7
4 PCIe x1
9
GND GND
10 10
GND GND
9
2 USB 2.0
11 PEx1_1Tp PEx1_0Tp 12 12 PEx1_0Tp PEx1_1Tp 11
1 SMB
13 PEx1_1Tn PEx1_0Tn 14 14 PEx1_0Tn PEx1_1Tn 13
xxx
Misc.
15
GND GND
16 16
GND GND
15
xxx
Pw r / Gn d
17 PEx1_2Tp PEx1_3Tp 18 18 PEx1_3Tp PEx1_2Tp 17
19 PEx1_2Tn PEx1_3Tn 20 20 PEx1_3Tn PEx1_2Tn 19
21
GND GND
22 22
GND GND
21
23 PEx1_1Rp PEx1_0Rp 24 24 PEx1_0Rp PEx1_1Rp 23
25 PEx1_1Rn PEx1_0Rn 26 26 PEx1_0Rn PEx1_1Rn 25
27
GND GND
28 28
GND GND
27
29 PEx1_2Rp PEx1_3Rp 30 30 PEx1_3Rp PEx1_2Rp 29
31 PEx1_2Rn PEx1_3Rn 32 32 PEx1_3Rn PEx1_2Rn 31
33
GND GND
34 34
GND GND
33
35 PEx1_1Clkp PEx1_0Clkp 36 36 PEx1_0Clkp PEx1_1Clkp 35
37 PEx1_1Clkn PEx1_0Clkn 38 38 PEx1_0Clkn PEx1_1Clkn 37
39
+5V_SB +5V_SB
40 40
+5V_SB +5V_SB
39
41 PEx1_2Clkp PEx1_3Clkp 42 42 PEx1_3Clkp PEx1_2Clkp 41
43 PEx1_2Clkn PEx1_3Clkn 44 44 PEx1_3Clkn PEx1_2Clkn 43
45
DIR PWRGOOD
46 46
PWRGOOD DIR
45
47 SMB_DAT
Reserved
48 48
Reserved
SMB_DAT 47
49 SMB_CLK
Reserved
50 50
Reserved
SMB_CLK 49
51 SMB_ALERT PSON# 52 52 PSON# SMB_ALERT 51
Toward edge of board
Toward center of board
Bottom View Signal AssignmentTop View Signal Assignment
+5 Volts
Bank 1
+5 Volts
Toward center of board
2.4.1 Type 1 x16 PCI Express Link
Type 1 connector banks 2 and 3 provide an x16 PCI Express link. The x16 Link allows maximum flexibility,
configurability, and expandability for current and future designs. Some examples of x16 Link application are next
generation graphics chips, 1/10 gigabit Ethernet chips, or use with a PCI Express Switch which can then branch the high
throughput out into any number of various size Links including multiple x16 Link graphics engines. The only limitation
is the bandwidth requirement for each of the branched links.
The specification allows the x16 Link on a Type 1 PCIe/104 to be configured for alternate PCI Express configurations.
These include two x8 Links, two x4 Links, or an Alternate Function defined by the CPU/chipset. These alternate
configurations are Host and Device dependent. A Host that supports an x16 Link is not required to support an Alternate
Function, two x8, or two x4 Links. Also, a device that supports operation at x16 is not required to support operation at x8
or x4.
2.4.1.1 Two x8 or x4 Links
Two x8 or two x4 PCI Express links can be provided on the x16 Link connectors pins. When a Device uses one of the
Links, the other Link is shifted according to the same rules as the x1 Links. With host support, each x8 Link may also be
used as an x4 Link.
Because there is only one clock provided for the x16 Link and potentially two devices when operating as x8 or x4, any
Device that operates at x8 or x4 must re-drive the clock. The clock must not incur more than 10ns of phase delay when it
is re-driven.
The pin assignments for the x8 and x4 Links are shown in Table 2-6 below.
Table 2-6: x16 Link as Two x8 or Two x4 Links Top Connector
Host Transmit Signals Host Receive Signals
x16 Signal x8 Signal x4 Signal x16 Signal x8 Signal x4 Signal
PEx16_0T(0) PEx8_0T(0) PEx4_0T(0) PEx16_0R(0) PEx8_0R(0) PEx4_0R(0)
PEx16_0T(1) PEx8_0T(1) PEx4_0T(1) PEx16_0R(1) PEx8_0R(1) PEx4_0R(1)
PEx16_0T(2) PEx8_0T(2) PEx4_0T(2) PEx16_0R(2) PEx8_0R(2) PEx4_0R(2)
PEx16_0T(3) PEx8_0T(3) PEx4_0T(3) PEx16_0R(3) PEx8_0R(3) PEx4_0R(3)
PEx16_0T(4) PEx8_0T(4) PEx16_0R(4) PEx8_0R(4)