Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 11
in parenthesis, for the links that have more than one lane. Last is “p” or “n” for the positive and negative signal in the
differential pair.
For example, Pex4_0T(2)p is the positive signal in lane number 2 of the first x4 Link.
A signal on the connector is designated “transmit” or “receive” in a Host-centric manner. The “transmit” pin on the Host
connects to the “T” (transmit) pin of the connector. From there, the signal connects to “receive” pin of the Device.
In a PCI Express system the transmit pins of the chip are always connected to the receive pins of the other chip in the link,
and vice-versa. For example, for a specific link, transmit on the Host chip is connected to receive on the Device chip, and
receive on the Host is connected to transmit on the Device.
Other non-PCI Express signals follow a similar convention.
2.4. Pin Assignment
On both of these connectors, the odd-numbered pins are located towards the edge of the board, and the even numbered
pins are located towards the inside of the board. Signals were assigned to pins to simplify breakout and reduce trace
lengths of the PCI Express signals around Connector A. See Table 2-3 for Type 1 and Table 2-4 for Type 2 pin
assignments.