Specifications
PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 10
2.2.2 PCIe/104 Type 2
Table 2-2 Connector A Type 2 Signals
Group Pins Signal Name Host Direction Description
PCIe x1
4 PEx1_[0:3]Tp Output Transmit Differential Upper Line for x1 Links 0, 1, 2, 3. Shifted when used.
4 PEx1_[0:3]Tn Output Transmit Differential Lower Line for x1 Links 0, 1, 2, 3. Shifted when used.
4 PEx1_[0:3]Rp Input Receive Differential Upper Line for x1 Links 0, 1, 2, 3. Shifted when used.
4 PEx1_[0:3]Rn Input Receive Differential Lower Line for x1 Links 0, 1, 2, 3. Shifted when used.
4 PEx1_[0:3]CLKp Output Clock Differential Upper Line for x1 Links 0, 1, 2, 3. Shifted when used.
4 PEx1_[0:3]CLKn Output Clock Differential Lower Line for x1 Links 0, 1, 2, 3. Shifted when used.
PCIe x4
8 PEx4_[0:1]T(#)p Output
Transmit Differential Upper Lines for the x4 Links. The x4 Links should be shifted
when used.
8 PEx4_[0:1]T(#)n Output
Transmit Differential Lower Lines for x4 Links. The x4 Links should be shifted when
used.
8 PEx4_[0:1]R(#)p Input
Receive Differential Upper Lines for the x4 Links. The x4 Links should be shifted
when used.
8 PEx4_[0:1]R(#)n Input
Receive Differential Lower Lines for the x4 Links. The x4 Links should be shifted
when used.
1 PEx16_x8_x4_CLKp Output Clock Differential Upper Line for x16 or first x8 or x4 Link. Re-driven when used
1 PEx16_x8_x4_CLKn Output Clock Differential Lower Line for x16 or first x8 or x4 Link. Re-driven when used
SATA
4 SATA_T[0:1]p Output Transmit Differential Upper Line for SATA Links 0 and 1. Shifted when used.
4 SATA_T[0:1]n Output Transmit Differential Lower Line for SATA Links 0 and 1. Shifted when used.
4 SATA_R[0:1]p Input Receive Differential Upper Line for SATA Links 0 and 1. Shifted when used.
4 SATA_R[0:1]n Input Receive Differential Lower Line for SATA Links 0 and 1. Shifted when used.
2 SATA_DET#[0:1] Input
Active low input to the host to indicate that a drive is attached. Only used in hot-
pluggable applications. Pull up to +3.3V at the host. Ground at the device when it is
attached. High impedance at the device when it is not attached, or when the drive is
going to be removed. Shifted along with the other SATA signals. Optional.
2 SATA_PWREN#[0:1] Output
Active low output from the host to enable power to the device. Only used in hot-
pluggable applications. Pull up to +3.3V at the device. Assert low at the host when the
device is to be powered (i.e. in response to SATA_DET# being asserted). Shifted along
with the other SATA signals. Optional.
Stacking
Control
1 STK0/WAKE# Input Stacking bit 0/Wake on LAN
1 STK1/SDVO_DAT In/Out Stacking bit 1/SDVO Data
1 STK1/PEG_ENA# Input Stacking bit 2/x16 Link or Alternate Function Enable
USB 2.0
2 USB_[1:0]p
Bidirectional
Differential Upper Lines for USB 2.0 Links 0, 1. Shifted when used.
2 USB_[1:0]n Differential Lower Lines for USB 2.0 Links 0, 1. Shifted when used.
1 USB_OC Input Over-current detect for USB. Pulled low by device.
USB 3.0
2 SSTX_[0:1]p Output Transmit Differential Upper Line for USB 3.0 Links 0, 1. Shifted when used.
2 SSTX _[0:1]n Output Transmit Differential Lower Line for USB 3.0 Links 0, 1. Shifted when used.
2 SSRX _[0:1]p Input Receive Differential Upper Line for USB 3.0 Links 0, 1. Shifted when used.
2 SSRX _[0:1]n Input Receive Differential Lower Line for USB 3.0 Links 0, 1. Shifted when used.
Misc. 1 DIR Output Direction indicates to the Device if it is installed above or below the Host
PCIe 1 PERST# Output Reset for PCI Express Bus
ATX
Power
Supply
1 PSON# Output Power Supply On brings the ATX power supply out of sleep mode.
1 PWRGOOD Input Power Good from the power supply indicates power is good
2 +5V_SB Power Standby Power for advanced power saving modes. Always on
2 +5V Power +5V central power planes
2 +3.3V Power +3.3V power
1 +12V Power +12V central power plane
1 RTC_Battery Power Battery for real time clock (with diode, series resistor, and capacitor)
46 GND Power GND pins
SMB
1 SMB_Clk Output Clock for SMBus
1 SMB_Data Bidirectional Data for SMBus
1 SMB_Alert# Input Alert for SMBus
Reserved 4 Reserved Reserved – Do not make any connection to these pins
# indicates the lane within a link
[0:3] indicates link 0, 1, 2, or 3
[0:1] indicates link 0 or 1
Table 2-2 Connector A Type 2 Signals shows only the required pins, arranged in functional groups, for the various buses
housed in Connector A Type 2. This version of the stackable PCI Express is as defined in the PCIe Base Specification
Revision 1.1 with the exception that Hot plug present detect, Hot plug detect, and JTAG are not supported.
2.3. Signal Naming Convention
The PCI Express signals on Connector A are named so that signal groupings are obvious. The fields in a signal name go
from general to specific. The PCI Express signals start with the characters “PE,” followed by the width of the Link (“x1”,
“x4”, “x8”, or “x16”), followed by an underscore “_”. Next is the Link number if there is more than one Link of that
width. Then is either “T”, “R”, or “Clk” for Transmit, Receive, or Clock respectively. Next is the lane number in the link