Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 9
2.2. Signal Descriptions
2.2.1 PCIe/104 Type 1
Table 2-1 Connector A Type 1 Signals
Group
Pins Signal Name Host Direction Description
PCIe x1
4 PEx1_[0:3]Tp Output Transmit Differential Upper Line for x1 Links 0, 1, 2, 3. Shifted when used.
4 PEx1_[0:3]Tn Output Transmit Differential Lower Line for x1 Links 0, 1, 2, 3. Shifted when used.
4 PEx1_[0:3]Rp Input Receive Differential Upper Line for x1 Links 0, 1, 2, 3. Shifted when used.
4 PEx1_[0:3]Rn Input Receive Differential Lower Line for x1 Links 0, 1, 2, 3. Shifted when used.
4 PEx1_[0:3]CLKp Output Clock Differential Upper Line for x1 Links 0, 1, 2, 3. Shifted when used.
4 PEx1_[0:3]CLKn Output Clock Differential Lower Line for x1 Links 0, 1, 2, 3. Shifted when used.
PCIe x4
8 PEx4_[0:1]T(#)p Output
Transmit Differential Upper Lines for the x4 Links. The x4 Links should be shifted
when used.
8 PEx4_[0:1]T(#)n Output
Transmit Differential Lower Lines for x4 Links. The x4 Links should be shifted when
used.
8 PEx4_[0:1]R(#)p Input
Receive Differential Upper Lines for the x4 Links. The x4 Links should be shifted
when used.
8 PEx4_[0:1]R(#)n Input
Receive Differential Lower Lines for the x4 Links. The x4 Links should be shifted
when used.
1 PEx16_x8_x4_CLKp Output Clock Differential Upper Line for x16 or first x8 or x4 Link. Re-driven when used
1 PEx16_x8_x4_CLKn Output Clock Differential Lower Line for x16 or first x8 or x4 Link. Re-driven when used
PCIe x16 or
PCIe x8
16
16
PEx16_0T(#)p
PEx8_[0:1]T(#)p Output
Transmit Differential Upper Lines for the x16, x8 or the x4 Links. The x8 Links should
be shifted when used.
16
16
PEx16_0T(#)n
PEx8_[0:1]T(#)n
Output
Transmit Differential Lower Lines for x16, x8 or the x4 Links. The x8 Links should be
shifted when used.
16
16
PEx16_0R(#)p
PEx8_[0:1]R(#)p
Input
Receive Differential Upper Lines for the x16, x8, or the x4 Links. The x 8 Links should
be shifted when used.
16
16
PEx16_0R(#)n
PEx8_[0:1]R(#)n
Input
Receive Differential Lower Lines for the x16, x8, or the x4 Links. The x8 Links should
be shifted when used.
1 PEx16_x8_x4_CLKp Output Clock Differential Upper Line for x16 or first x8 or x4 Link. Re-driven when used
1 PEx16_x8_x4_CLKn Output Clock Differential Lower Line for x16 or first x8 or x4 Link. Re-driven when used
Stacking
Control
1 STK0/WAKE# Input Stacking bit 0/Wake on LAN
1 STK1/SDVO_DAT In/Out Stacking bit 1/SDVO Data
1 STK1/PEG_ENA# Input Stacking bit 2/x16 Link or Alternate Function Enable
USB 2.0
2 USB_[1:0]p
Bidirectional
Differential Upper Lines for USB 2.0 Links 0, 1. Shifted when used.
2 USB_[1:0]n Differential Lower Lines for USB 2.0 Links 0, 1. Shifted when used.
1 USB_OC Input Over-current detect for USB. Pulled low by device.
Misc. 1 DIR Output
Direction indicates to the Device if it is installed above or below the Host. Bypass with
a 0.01uF capacitor to ground as close as possible to the pin.
PCIe 1 PERST# Output Reset for PCI Express Bus
ATX
Power
Supply
1 PSON# Output
Power Supply On brings the ATX power supply out of sleep mode. Bypass with a
0.01uF capacitor to ground as close as possible to the pin.
1 PWRGOOD Input
Power Good from the power supply indicates power is good Bypass with a 0.01uF
capacitor to ground as close as possible to the pin.
2 +5V_SB Power
Standby Power for advanced power saving modes. Always on Bypass with a 0.01uF
capacitor to ground as close as possible to the pin.
2 +5V Power +5V central power planes
2 +3.3V Power +3.3V power
1 +12V Power +12V central power plane
46 GND Power GND pins
SMB
1 SMB_Clk Output Clock for SMBus
1 SMB_Data Bidirectional Data for SMBus
1 SMB_Alert# Input Alert for SMBus
# indicates the lane within a link
[0:3] indicates link 0, 1, 2, or 3
[0:1] indicates link 0 or 1
Table 2-1 shows only the required pins, arranged in functional groups, for the various buses housed in Connector A Type 1.
This version of the stackable PCI Express is as defined in the PCIe Base Specification Revision 1.1 with the exception that
Hot plug present detect, Hot plug detect, and JTAG are not supported.