Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 6
1.9.5 System Management Bus
The optional System Management Bus (SMBus) is a two-wire interface through which various system component chips
can communicate with each other and with the rest of the system. It is based on the principles of operation of I2C. SMBus
provides a control bus for system- and power-management related tasks. A system may use SMBus to pass messages to
and from devices instead of tripping individual control lines. Removing the individual control lines reduces pin count.
Accepting messages ensures future expandability. With SMBus, a device can provide manufacturer information, tell the
system what its model/part number is, save its state for a suspended event, report different types of errors, accept control
parameters, and return its status. SMBus is described in System Management Bus (SMBus) Specification, Version 2.0.
Refer to this specification for DC characteristics and all AC timings. If the system board or add-in card supports SMBus,
it must adhere to additional requirements that may be found in Chapter 8 of the PCI Local Bus Specification, Revision.
3.0.
An address resolution protocol (ARP) is defined in the SMBus 2.0 Specification that is used to assign slave addresses to
SMBus devices. Although optional in the SMBus 2.0 Specification, it is required that systems that connect the SMBus to
PCI slots implement ARP for assignment of SMBus slave addresses to SMBus interface devices on PCI add-in cards. The
system must execute ARP on a logical SMBus whenever any PCI bus segment associated with the logical SMBus exits
the B3 state or a device in an individual slot associated with the logical SMBus exits the D3cold state. Prior to executing
ARP, the system must insure that all ARP-capable SMBus interface devices are returned to their default address state.
The system board provides pull-ups to the +3.3Vaux rail per the above specification and the components attached to these
signals need to have a 3.3V signaling tolerance (5V signaling must not be used). Also, the SMBus is used during all
power states, so all components attached to the SMBus must remain powered during standby, or ensure that the bus is not
pulled down when not powered.
The SMBus interface is based upon the System Management Bus Specification (SMBus 2.0 Specification). This two-wire
serial interface has low power and low software overhead characteristics that make it well suited for low-bandwidth
system management functions.
The capabilities enabled by the SMBus interface include, but are not limited to, the following:
Support for client management technologies.
Support for server management technologies.
Support for thermal sensors and other instrumentation devices on add-in cards.
Add-in card identification when the bus is in the B3 state or when the PCI device is in the D3hot or D3cold
states as defined in the PCI Power Management Interface Specification.
1.9.6 ATX and Power Management
PCI/104-Express and PCIe/104 incorporate all of the necessary control and signal lines for ATX and power management
functionalities. These signals include PWRGOOD, PSON#, +5V_SB, and PME#. The inclusion of these signals allows
maximum power savings.
PWRGOOD is a “power good” signal. It should be asserted high by the power supply to indicate that the +12 VDC, +5
VDC, and +3.3 VDC outputs are above the under-voltage thresholds and that sufficient main energy is stored by the
converter to guarantee continuous power operation within specifications. Conversely, PWRGOOD should be de-asserted
to a low state when any of the +12 VDC, +5 VDC, or +3.3 VDC output voltages falls below its under-voltage threshold,
or when main-power has been removed for a sufficiently long enough time that the power supply operation cannot be
guaranteed beyond the power-down warning time.
PSON# is an active-low, TTL-compatible signal that allows a motherboard to remotely control the power supply in
conjunction with features such as soft on/off, wake-on-LAN, or wake-on-modem. When PSON# is pulled to TTL low, the
power supply should turn on the five main DC output rails: +12 VDC, +5 VDC, +3.3 VDC, -5 VDC, and -12 VDC. When
PSON# is pulled to TTL high or open-circuited, the DC output rails should not deliver current and should be held at zero
potential with respect to ground. PSON# has no effect on the +5V_SB output, which is always enabled whenever AC
power is present. PSON# shall be pulled to +5V_SB with a 10K ohm resistor on the power supply.
+5V_SB is a standby supply output that is active whenever AC power is present. It provides a power source for circuits
that must remain operational when the five main DC output rails are in a disabled state. Example uses include soft power
control, wake-on-LAN, wake-on-modem, intrusion detection, or suspend state activities.