Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 5
PCI/104-Express and PCIe/104 incorporate four x1 PCI Express Links and options for either a single x16 Link, or two x8
Links, or two x4 PCI Express Links to allow connections to standard PCI Express device chips. The x16 Link option
allows maximum flexibility, configurability, and expandability for current and future designs. Some examples of x16
Link application are next generation graphics chips, 1/10 gigabit Ethernet chips, or use with a PCI Express Switch which
can then branch the high throughput out into any number of various size Links including multiple x16 Link graphics
engines. The only limitation is the bandwidth requirement for each of the branched links.
1.9.1.1 PCI Express x16 or PEG Link
PCI Express x16, sometimes called PEG (PCI Express for Graphics), is an interface with 16 PCI Express differential
lanes to connect a high performance video controller or other high bandwidth devices. In chipsets with internal graphics,
the PEG bus is used as an alternative to connect an external video controller. The internal chip controller is disabled in
this case. The PEG-Bus configuration must be enabled from the Device by connecting the PEG-ENA# signal to ground.
1.9.1.2 Non-PCI Express functions of the CPU/Chipset x16 Link
Some processors/chipsets allow alternate functions on the x16 link pins. There is no standard which all manufacturers
follow, so this specification will not define one. Using these alternate functions is allowed, but it is up to the host board
manufacturer to define the alternate uses and what peripheral boards are compatible. Use of the PEG-ENA# shall remain
open on these peripheral boards.
One example of this is Serial Digital Video Output (SDVO). This bus is provided as an alternative to the PEG-Bus on
some CPU chipsets. SDVO-Links needs up to 7 differential signal pairs per interface.
1.9.2 SATA Links
Serial ATA (SATA or Serial Advanced Technology Attachment) is a computer bus interface for connecting host bus
adapters to mass storage devices such as hard disk drives and optical drives. Serial ATA was designed to replace the older
ATA (AT Attachment) standard (also known as EIDE). It is able to use the same low level commands, but serial ATA
host-adapters and devices communicate via a high-speed serial cable over two pairs of conductors. Support for device
detection and power enable for hot-pluggable applications.
1.9.3 LPC Bus
The Low Pin Count bus, or LPC bus, is used on IBM-compatible personal computers to connect low-bandwidth devices
to the CPU, such as the boot ROM and the “legacy” I/O devices. The “legacy” I/O devices usually include serial and
parallel ports, keyboard, mouse, and floppy disk controller.
The LPC bus was introduced by Intel in 1998 as a substitute for the Industry Standard Architecture (ISA) bus. It
resembles ISA to software, although physically it is quite different, replacing the 16-bit-wide, 8.33 MHz ISA bus with a
4-bit-wide bus operating at 4 times the clock speed (33.3 MHz). LPC’s main advantage is that it requires only seven
signals.
1.9.4 Universal Serial Bus (USB)
The USB is specified to be an industry-standard extension to the PC architecture with a focus on PC peripherals that
enable consumer and business applications. The following criteria were applied in defining the architecture for the USB:
• Ease-of-use for PC peripheral expansion.
• USB 2.0 is a low-cost solution that supports transfer rates up to 480Mb/s.
• USB 3.0 is a high-speed solution with speeds up to 4800Mb/s
• Full support for real-time data of voice, audio, and video.
• Protocol flexibility for mixed-mode isochronous data transfers and asynchronous messaging.
• Integration in commodity device technology.
• Comprehension of various PC configurations and form factors.
• Provision of a standard interface capable of quick diffusion into a product.
• Enabling new classes of devices that augment the PC’s capability.
• Full backward compatibility of USB 2.0 for devices built to previous versions of the specification.
The over-current protection is made on each PCI/104-Express peripheral board, if needed. Any channel can pull the OC#-
Signal low to indicate the CPU host that an over-current situation has occurred.