Specifications

PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 9
TABLE OF TABLES
Table 1-1 Feature Summary ........................................................................................................................... 2
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Table 1-2 Type 1 & Type 2 Combinations ..................................................................................................... 4
Table 2-1 Connector A Type 1 Signals .......................................................................................................... 9
Table 2-2 Connector A Type 2 Signals ........................................................................................................ 10
Table 2-3 Connector A, Type 1 Pin Assignments ........................................................................................ 12
Table 2-4 Connector A, Type 2 Pin Assignments ........................................................................................ 13
Table 2-5 Connector A, OneBank Pin Assignments .................................................................................... 14
Table 2-6: x16 Link as Two x8 or Two x4 Links Top Connector ................................................................ 14
Table 2-7: x16 Link as Two x8 or Two x4 Links Bottom Connector .......................................................... 15
Table 2-8: Signal Switches or equivalent ..................................................................................................... 21
Table 2-9: Via and Trace Length Budget ..................................................................................................... 22
Table 2-10 PCI Express and USB 3.0 Routing Specification ....................................................................... 23
Table 2-11 SATA Routing Specification ..................................................................................................... 24
Table 3-1 Connector B Signals ..................................................................................................................... 29
Table 3-2 Connector Signal Assignment ...................................................................................................... 30
Table 4-1 Required Host State When Peripherals Are Placed on Type 1 and Type 2 Hosts ........................ 32
Table 4-2 Peripheral Effect on Type 1 Host CPU Signals ............................................................................ 32
Table 4-3 Peripheral Effect on Type 2 Host CPU Signals ............................................................................ 32
Table 4-4 Host CPU Stacking Rules ............................................................................................................ 33
Table 4-5 Required Host Connector A Pin Configuration ............................................................................ 33
Table 4-6 Peripheral Stacking Rules ............................................................................................................ 33
Table 5-1 Connector A Power Delivery (OneBank Option) ........................................................................ 40
Table 5-2 Connector B Power Delivery ....................................................................................................... 40
Table 5-3 Connector A Power Delivery ....................................................................................................... 41
Table 5-4 Combined Connector A and B Power Delivery ........................................................................... 41