Specifications

ManualsBrandsMaxim ManualsComputer equipment/MAX4889A

PCI/104-Express

™

PCIe/104

™

Specification

Including OneBank

™

and Adoption on

104

™

, EPIC

™

, and EBX

™

Form Factors

Version 3.0

February 17, 2015

Please Note:

This specification is subject to change without notice. While every effort has been made to ensure the

accuracy of the material contained within this document, the PC/104 Consortium shall under no

circumstances be liable for incidental or consequential damages or related expenses resulting from the use

of this specification. If errors are found, please notify the PC/104 Consortium.

The PC/104 logo, PC/104, PC/104-Plus, PCI-104, PCIe/104, PCI/104-Express, 104, OneBank, EPIC

and EBX are trademarks of the PC/104 Consortium. All other marks are the property of their respective

companies.

Summary of content (73 pages)

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™ PCI/104-Express & ™ PCIe/104 Specification Including OneBank™ and Adoption on 104™, EPIC™, and EBX™ Form Factors Version 3.0 February 17, 2015 Please Note: This specification is subject to change without notice. While every effort has been made to ensure the accuracy of the material contained within this document, the PC/104 Consortium shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this specification.
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IMPORTANT INFORMATION AND DISCLAIMERS The PC/104 Consortium (“Consortium”) makes no warranties with regard to this PCI/104-Express and PCIe/104 Specifications (“Specifications”) and, in particular, neither warrant nor represent that these Specifications or any products made in conformance with them will work in the intended manner.
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REVISION HISTORY March 21, 2008 • Version 1.0 Initial release March 27, 2009 • • • • • Version 1.1 Add USB and over current signal to pin out, inserted description in 1.4.4, modified shift example to include USB Section 2.4 corrected that even numbered pins are located towards the inside of the board and odd numbered pins are located towards the edge of the board PEx16_ENA changed to PEG_ENA# in section 2.4.1.2 and 2.4.3 Figure 2.
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December 16, 2014 • • • • Version 3.0 Added OneBank™ connector variation Updated connector mechanical performance specifications Cleaned up Link Shifting wording Added stitching capacitors to first bank of PCIe/104 connector PCIe/104 and PCI/104-Express Specification Revision 3.
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TABLE OF CONTENTS 1. INTRODUCTION ................................................................................................................................................... 1 1.1. Purpose ...................................................................................................................................................... 1 1.2. Standard Identification ............................................................................................................................... 1 1.
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2.4.2 PEG_ENA# Signal................................................................................................................. 15 2.4.3 DIR Signal ............................................................................................................................. 15 2.4.4 Stack-UP or Stack-DOWN Link Shifting .............................................................................. 17 2.4.5 Link Shifting PCB Examples ...............................................................
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5. ELECTRICAL SPECIFICATION......................................................................................................................... 40 5.1. Power and Ground ................................................................................................................................... 40 5.1.1 Connector A, PCIe/104, Power Capabilities .......................................................................... 40 5.1.2 Connector B, PCI-104, Power Capabilities............................
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TABLE OF FIGURES Figure 1-1: PCI/104-Express and PCIe/104 Board Layouts on 104 Form Factor .......................................... 1 Figure 1-2: OneBank Connector PCI/104-Express and PCIe/104 Board Layouts on 104 Form Factor......... 2 Figure 1-3 RTC Battery Example ................................................................................................................... 7 Figure 2-1 Required Circuitry for a Host Module Configuration for Automatic Link Shifting ...................
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Figure 6-10 Optional OneBank 0.866” (22mm) Connector ASP-142781-07 or equivalent Mechanical Drawings ............................................................................................................................................. 48 Figure 6-11: Standard ASP-129646-03 or equivalent Mechanical Drawings .............................................. 49 Figure 6-12 Optional OneBank ASP-129646-22 or equivalent Mechanical Drawings ................................
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TABLE OF TABLES Table 1-1 Feature Summary ........................................................................................................................... 2 Table 1-2 Type 1 & Type 2 Combinations ..................................................................................................... 4 Table 2-1 Connector A Type 1 Signals .......................................................................................................... 9 Table 2-2 Connector A Type 2 Signals ..................
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Glossary of Terms Terms Definitions ATX Advanced Technology Extended A specification for PC motherboards, power supplies, and system chassis. One of its most notable features is support for “Standby” and “Soft-Off” power savings modes. Device A logical device attached to a PCI Express Link. Generally an add-in card. DMA Direct Memory Access A method for peripherals to efficiently access system memory without CPU intervention.
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1. INTRODUCTION 1.1. Purpose This document defines the addition of PCI Express, the next generation serial interconnect bus, to the stackable 104, EPIC, and EBX form factors. PCI Express was chosen because of its performance, scalability, wide market acceptance, and growing silicon availability worldwide.
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A reduced feature set OneBank version does not implement the Bank 2 or Bank 3 connectors. Figure 1-2 shows the same basic views with the OneBank connector. D1 C1 B1 A1 PCI Bus: 32 bit/33MHz 3.775 inches (95.89 mm) 3.775 inches (95.89 mm) Connector B PCI – 120 Pin Connector PCI/104-Express Module 1-Bank Connector PCIe/104 Module 1-Bank Connector Connector A PCI Express – 52 pin Connector Connector A PCI Express – 52 pin Connector Bank 1 Bank 1 3.550 inches (90.17 mm) 3.550 inches (90.
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1.4.2 PCI/104-Express Version 1.0 and 1.1 Peripheral Board Compatibility All PCI Express x1, USB 2.0, and SMBus boards build to version 1.0 or 1.1 are considered Universal boards and will work unchanged on either Type 1 or Type 2 host CPUs. PCI Express x16 peripherals work only on Type 1 hosts. USB 3.0, SATA, and LPC peripherals will work only on Type 2 hosts. The pin assignments on Bank 1 of the connector is exactly the same in Type 1 and Type 2, therefore all the PCI Express x1, USB 2.
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• 6. SATA 1 at 1.5 Gigabits/second 7. USB 2.0 at 480 Mbits/second Follow the guidelines for up and down stacking in Table 1-2 Type 1 & Type 2 Combinations below. For example, if you have a host with a Type 1 stacking down and a Type 2 stacking up with one SATA 2, one USB 3.0, one PCI Express x1 Gen 2, two PCI Express x1 Gen 1, and one PCI Express x16 Gen 2 peripherals your stack could be configured as: • • • • • • • SATA peripheral USB 3.
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PCI/104-Express and PCIe/104 incorporate four x1 PCI Express Links and options for either a single x16 Link, or two x8 Links, or two x4 PCI Express Links to allow connections to standard PCI Express device chips. The x16 Link option allows maximum flexibility, configurability, and expandability for current and future designs.
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1.9.5 System Management Bus The optional System Management Bus (SMBus) is a two-wire interface through which various system component chips can communicate with each other and with the rest of the system. It is based on the principles of operation of I2C. SMBus provides a control bus for system- and power-management related tasks. A system may use SMBus to pass messages to and from devices instead of tripping individual control lines. Removing the individual control lines reduces pin count.
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1.9.7 RTC Battery Any board in a system can provide a 3.0 to 3.6 volt battery on pin 154 of the Type 2 connector. This battery shall be current limited with a 1KΩ resistor, reverse current protected with a schottky diode, and filtered with a 10uF capacitor. Any board in the system may use the battery. Battery life will depend on the specific battery used and the load. Figure 1-3 RTC Battery Example 1.9.
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2. EXPANSION CONNECTOR A 2.1. Functions Not all processors and chipsets support all features on the PCIe/104 connectors, and in some cases the design of the Host may consume some or all of these features, rendering them unavailable. It is up to the Host designer to determine the type and number of features included on the expansion connector. For cases where the host provides less than the maximum number of features supported by the connector, see Section 2.4.4. 2.1.
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2.2. Signal Descriptions 2.2.
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2.2.2 PCIe/104 Type 2 Table 2-2 Connector A Type 2 Signals Group PCIe x1 PCIe x4 SATA Stacking Control USB 2.0 USB 3.0 Misc.
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in parenthesis, for the links that have more than one lane. Last is “p” or “n” for the positive and negative signal in the differential pair. For example, Pex4_0T(2)p is the positive signal in lane number 2 of the first x4 Link. A signal on the connector is designated “transmit” or “receive” in a Host-centric manner. The “transmit” pin on the Host connects to the “T” (transmit) pin of the connector. From there, the signal connects to “receive” pin of the Device.
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Table 2-3 Connector A, Type 1 Pin Assignments Bottom View Signal Assignment 1 USB_OC# PE_RST# 2 2 PE_RST# USB_OC# 3 3.3V 3.3V 4 4 3.3V 3.3V 3 5 USB_1p USB_0p 6 6 USB_0p USB_1p 5 7 USB_1n USB_0n 8 8 USB_0n USB_1n 7 PCIe x16 9 GND GND 10 10 GND GND 9 2 USB 2.0 11 PEx1_1Tp PEx1_0Tp 12 12 PEx1_0Tp PEx1_1Tp 11 13 PEx1_1Tn PEx1_0Tn 14 14 PEx1_0Tn PEx1_1Tn 13 xxx Misc.
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Table 2-4 Connector A, Type 2 Pin Assignments Top View Signal Assignment USB_OC# PE_RST# 2 2 PE_RST# USB_OC# 3 3.3V 3.3V 4 4 3.3V 3.3V 3 5 USB_1p USB_0p 6 6 USB_0p USB_1p 5 7 USB_1n USB_0n 8 8 USB_0n USB_1n 7 2 PCIe x4 9 GND GND 10 10 GND GND 9 2 USB 2.0 11 PEx1_1Tp PEx1_0Tp 12 12 PEx1_0Tp PEx1_1Tp 11 2 USB 3.
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Table 2-5 Connector A, OneBank Pin Assignments Top View Signal Assignment 2.4.1 Bottom View Signal Assignment 1 USB_OC# PE_RST# 2 2 PE_RST# USB_OC# 3 3.3V 3.3V 4 4 3.3V 3.3V 1 3 5 USB_1p USB_0p 6 6 USB_0p USB_1p 5 7 USB_1n USB_0n 8 8 USB_0n USB_1n 7 4 PCIe x1 9 GND GND 10 10 GND GND 9 2 USB 2.0 11 PEx1_1Tp PEx1_0Tp 12 12 PEx1_0Tp PEx1_1Tp 11 13 PEx1_1Tn PEx1_0Tn 14 14 PEx1_0Tn PEx1_1Tn 13 xxx Misc.
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Table 2-6: x16 Link as Two x8 or Two x4 Links Top Connector Host Transmit Signals x16 Signal x8 Signal x4 Signal PEx16_0T(5) PEx8_0T(5) PEx16_0T(6) PEx8_0T(6) PEx16_0T(7) PEx8_0T(7) PEx16_0T(8) PEx8_1T(0) PEx4_1T(0) PEx16_0T(9) PEx8_1T(1) PEx4_1T(1) PEx16_0T(10) PEx8_1T(2) PEx4_1T(2) PEx16_0T(11) PEx8_1T(3) PEx4_1T(3) PEx16_0T(12) PEx8_1T(4) PEx16_0T(13) PEx8_1T(5) PEx16_0T(14) PEx8_1T(6) PEx16_0T(15) PEx8_1T(7) Host Receive Signals x16 Signal x8 Signal x4 Signal PEx16_0R(5) PEx8_0R(5) PEx16_0R(6) PEx8_0R(
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2.4.3.1 DIR Line on Host DIR Link 0 Link 1 Link 2 Link 3 The state of the DIR line is always determined by the Host so that the Devices can be designed without regards to the design of other Devices. On the top side connector this line must be tied to ground on the Host. On the bottom side connector the DIR line must be tied to +5 volt power during all implemented power saving modes except power completely off.
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If the Device is stacked below the module, then the DIR line would be set to +5V and the SELECT line of the multiplexers would allow Link 3 to connect to the PCI device. Links 0, 1, and 2 are then allowed to shift and pass over so that Link 2 is in the Link 3 position, Link 1 is in the Link 2 position, and Link 0 is in the Link 1 position. A right-most link is now available for the next Device card to be stacked below the first Device.
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2.4.5 Link Shifting PCB Examples As a demonstration of link shifting in the presence of multiple link groups, the x1 PCI Express, x4 PCI Express, USB 2.0, USB 3.0, and SATA link groups are used in Figure 2-3: Automatic Link Shifting Examples for Host and Various Devices. Any Device may use one or more Links from any group. If multiple Links are used then the necessary link shifting must be implemented on the Device PCB for each Link and Link Group.
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2.4.
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CPU Four x 1 Links 1x1 2x1 3x1 Two x4 Links 4x1 0x4 0x4 0x4 0x4 1x4 1x4 1x4 1x4 x1 Link Device x4 Link Device X4 Link Peripheral Module Automatic Shift x4 Link Device X4 Link Peripheral Module Automatic Shift x1 Link Device x1 Link Peripheral Module Automatic Shift x1 Link Device x1 Link Peripheral Module Automatic Shift Figure 2-5: Automatic Link Shifting Stack-Down Example Consisting of Two x1 Link Device, One x4 Link Device, and One Device with One x1 Link and One x4 Link PCIe/104 and
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2.5. Switching To ensure that all Device modules can be stacked up or down without manual configuration a signal switch is required on the Device. The switch is only required on interface being used. For example a SATA Device will have a switch on the SATA link, but will not have switches on USB 3.0 or PCI Express links. 2.5.1 Signal Switch A signal switch is an analog multiplexer that can be used to select between the link on top connector or the bottom connector.
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2.7. Layout Recommendations The Data rate for PCI Express Generation 1 is 2.5 Gbps, Generation 2 is 5.0 Gbps, and Generation 3 is 8.0 Gbps. This means that significant frequency content exists up to 1.25 GHz for Generation 1, 2.50 GHz for Generation 2, and 4.0GHz for Generation 3. At these speeds, PCB layout becomes very critical.
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2.8. Routing Topology 2.8.1 PCI Express and USB 3.0 Figure 2-6 below shows the positioning of the DC blocking capacitor and PCIe/104 connector in relation to the Host and Device. The DC blocking capacitor is placed on the transmit signals. This will be the signals the Host drives onto the Tx bus connector’s pins and the signals the Device drives onto the Rx signals of the connector.
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2.8.2 SATA Figure 2-7 below shows the positioning of the DC blocking capacitor and PCIe/104 connector in relation to the Host and Device. The DC blocking capacitor is placed on the transmit and receive signals. The actual position is not critical; however the position must be closely matched between the signals of a differential pair. Note that a SATA device typically has internal capacitors, if so capacitors on the PCB are not required.
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2.9. Device Connector Break-out Examples These drawings are not to scale and do not show controlled impedance lines. They are intended to show the general connections and lane shifting on a device for various PCIe/104 devices that can be stacked above or below the CPU. All power, ground, and unused signals have the top and bottom connectors connected together. The examples show the device on the top of the board; however that is not a requirement. 2.9.
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2.9.3 Type 1 PCI Express x8 Device Layout Example Figure 2-10 below shows an example of routing a Type 1 x8 PCI Express link from the PCIe/104 connector directly to a PCI Express x8 device. This device is shown as a stack down version and implements lane shifting. Figure 2-10 Example breakout routing a PCI Express x8 device stacking down with lane shifting 2.9.
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2.9.5 Type 2 USB 3.0 Device Layout Example Figure 2-12 below shows an example of routing an USB 3.0 link from the PCIe/104 connector to a Signal Switch. This device can be stacked either above or below the CPU and implements lane shifting. USB 3.0 requires that each USB 3.0 port to be associated with a USB 2.0 port as shown in this example. Figure 2-12 Example breakout routing an USB 3.0 device with lane shifting 2.9.
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3. EXPANSION CONNECTOR B 3.1. Description Expansion Connector B is the stackable PCI Expansion connector of the PC/104-Plus and PCI-104 specifications. For full details and connector location see the PC/104-Plus or PCI-104 Specifications published by the PC/104 Consortium 3.2. Functions • • • Four 32 bit, 33 MHz PCI Bus Links each capable of Bus Mastering +5V_SB, PSON#, PME# for ATX power management Power: +3.3V, +5V, +12V, -12V PCIe/104 and PCI/104-Express Specification Revision 3.
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3.3. Signal Descriptions Table 3-1 Connector B Signals # Pins Signal Name 32 AD[31:00] 4 C/BE[0,3]# 1 PAR 1 FRAME# 1 TRDY# 1 IRDY# 1 STOP# 1 DEVSEL# 4 IDSEL[0,3] 1 LOCK# 1 1 4 4 PERR# SERR# REQ#[0,3] GNT#[0,3] 4 CLK[0,3] 1 RST# 1 M66EN 1 1 1 1 INTA# INTB# INTC# INTD# 1 PME# 1 +5V_SB 1 5 10 8 1 1 25 PSON# VI/O +3.3V +5V +12V -12V GND Group PCI Bus ATX Power Supply Power Description Address and Data are multiplexed on the same PCI pins.
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3.4. Pin Assignment Signals are assigned in the same relative order as in the PCI Local Bus Specification Revision 2.2, but transformed to the corresponding header connector pins. Because of the stack-through nature of the bus, slot-specific signals are duplicated for each plug-in module. The system has been designed to accommodate 4 modules, which are PC/104-Plus, PCI-104, or a combination of the two, so multiple sets of the signals have been duplicated to accommodate one signal for each module.
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3.6. PCI Signaling Voltage (VI/O) Requirements 3.6.1 PCI Host Module The PCI Host board will always determine the PCI signaling level on the bus by setting all VI/O pins to either +3.3V or +5V. If VI/O is set to 3.3V, then the system will use +3.3V I/O signaling and, likewise, if VI/O is set to +5V, then the system will use +5V I/O signaling. Some PCI host modules may only allow one of the options, while others may provide a jumper to allow the user to select the signaling level.
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4. PCIe/104 Type 1 and Type 2 Stacking 4.1. System Stacking Rules These rules will insure that the systems are not damaged when different type peripheral boards and host modules are stacked together. A 1-bank implementation is limited to the PCI Express x1and USB 2.0 features noted below; the STKx signals are not present.
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The signals that need special consideration are: SATA_T[0:3]n, SATA_T[0:3]p, SATA_R[0:3]n, SATA_R[0:3]p, SATA_DET#[0:3], SATA_PWREN#[0:3], LPC_CLK, LPC_AD[0:3], LPC_FRAME#, LPC_SERIRQ#, LPC_DRQ#. • • • The CPU SHALL NOT DRIVE these signals until it determines that there is not a Bus Stacking Error. If the system detects a bus stacking error, it must remain in reset and not drive these signals. The CPU must tolerate PCI Express signal levels on these signals during reset.
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4.4. Stack Configuration Examples Figure 4-1 illustrates a stack down configuration using PCI/104-Express and PCI-104 peripheral modules. In this configuration the Connector A, PCIe/104, could be either Type 1 or Type 2. PCI Memory Chipset PCI/104-Express CPU Module Processor Chip PCI PCI PCIe 0.600 inches (15.24 mm) PCIe Device PCI/104-Express Peripheral Module PCI PCIe 0.600 inches (15.24 mm) PCIe Device PCI/104-Express Peripheral Module PCI PCIe 0.600 inches (15.
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Figure 4-2 illustrates putting PCIe/104 and PCI/104-Express peripheral modules on an EPIC Host board. In this configuration Connector A, PCIe/104, could be either Type 1 or Type 2. PCIe Device PCIe/104 Peripheral Module PCIe 0.600 inches (15.24 mm) PCIe Device PCIe/104 Peripheral Module PCIe 0.600 inches (15.24 mm) PCIe Device PCIe/104 Peripheral Module PCIe 0.600 inches (15.24 mm) PCI PCI Device PCI/104-Express Peripheral Module PCI PCI PCIe Memory Chipset 0.600 inches (15.
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Figure 4-3 illustrates a stack with PCIe/104, PCI/104-Express and PCI-104 peripheral boards. In this configuration Connector A, PCIe/104, could be either Type 1 or Type 2. Memory PCIe/104 CPU Module Chipset Processor Chip PCIe 0.600 inches (15.24 mm) PCIe Device PCIe/104 Peripheral Module PCIe 0.600 inches (15.24 mm) PCIe Device PCIe/104 to PCI-104 Bridge Module PCI PCIe 0.600 inches (15.24 mm) PCI Device PCI-104 Peripheral Module PCI PCI 0.600 inches (15.
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Figure 4-4 illustrates a stack that has PCI/104-Express Host with the PCIe/104 bus connected top and bottom with PCIe/104, PC/104-Plus, and PCI-104 peripherals. In this configuration Connector A, PCIe/104, could be either Type 1 or Type 2. Because of the requirement that each type of bus must completely reside on one side of the Host in order to avoid bus splits and signal stubs, only PCI-104 and PCIe/104 modules can be used in this configuration.
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Figure 4-5 illustrates a Host with a PCIe/104 Type 1 connector going down and a PCIe/104 Type 2 connector going up. The Host does not have the top and bottom busses connected. Type 1 and Universal Devices are stacked below the Host. Type 2 and Universal Devices are stacked above the Host. PCIe x1 Device Type 2 PCIe/104 Universal PCIe x1 Peripheral Module Type 2 0.600 inches (15.24 mm) SATA Drive PCIe/104 Type 2 SATA Peripheral Module Type 2 0.600 inches (15.
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Figure 4-6 illustrates a Host with a PCIe/104 Type 2 connector going down and a PCIe/104 Type 2 connector going up. The Host does not have the top and bottom busses connected so, as in this example, it can support up to 4 SATA Devices. In this example Type 2 and Universal Devices are stacked either above or below the Host or both at the same time. Type 2 PCIe x1 Device PCIe/104 Type 2 SATA Peripheral Module Type 2 0.600 inches (15.24 mm) SATA Drive PCIe/104 Type 2 SATA Peripheral Module Type 2 0.
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5. ELECTRICAL SPECIFICATION 5.1. Power and Ground 5.1.1 Connector A, PCIe/104, Power Capabilities The power rails on Connector A are +5V_SB, +3.3V, +5V, and +12V. The +5V and +12V are carried on central conductor planes which are dispersed among the three banks of Connector A. The +5V_SB is carried on individual pins. The current carrying capacities of the central panes and pins are shown in Table 5-1 below. Current values include a 20% industry standard de-rating factor at 85 °C.
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5.1.3 Total PCIe/104 Power Capabilities Connector A Only (OneBank Option) Table 5-3 Connector A Power Delivery Voltage 5.1.4 Minimum Voltage (V) Maximum Voltage (V) Total Current (A) Total Power (W) +3.3V 3.00 3.60 3.6 (3.6) 11.9 (11.9) +5V 4.75 5.25 16.8 (8.4) 84.0 (42.0) +12V 11.40 12.60 8.4 (0.0) 100.8 (0.0) +5V_SB 4.75 5.25 3.6 (3.6) 18.0 (18.0) GND n/a n/a 82.8 (18.
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6. MECHANICAL SPECIFICATIONS 6.1. Connector A Samtec’s QMS/QFS High Speed Interface series connectors were optimized for a 0.600” (15.24mm) stacking height and standoff tolerances. Additionally, an optional 22mm top connector was developed to allow additional height above the board. In both height options the bottom connector remains the same. An equivalent connector can be used. It is permissible to use a OneBank connector for applications that do not require the signals or power in banks 2 and 3.
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Figure 6-4: Bottom Connector ASP-129646-03 or equivalent Figure 6-5: OneBank Bottom Connector ASP-129646-22 or equivalent Shown with Pick-and-Place Adapter Top Connector Bottom Connector Figure 6-6: Top Half and Bottom Half of Connector A Shown with Pick-and-Place Adapters PCIe/104 and PCI/104-Express Specification Revision 3.
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6.1.2 Connector A Specifications MATERIALS Housing: Terminal & Ground Plane Material: Terminal Plating: Plane Plating: Terminal and Plane Tails: Liquid Crystal Polymer Phosphor Bronze Au over 50μ” (1.27μm) Ni Au over 50μ” (1.
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6.1.3 Standard 0.600” (15.24mm) Top Connector A Mechanical Drawings Figure 6-7: Standard 0.600” (15.24mm) Connector ASP-129637-03 or equivalent Mechanical Drawings PCIe/104 and PCI/104-Express Specification Revision 3.
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6.1.4 Optional 0.866” (22.00mm) Top Connector A Mechanical Drawings Figure 6-8 Optional 0.866” (22.00mm) Connector ASP-142781-03 or equivalent Mechanical Drawings PCIe/104 and PCI/104-Express Specification Revision 3.
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6.1.5 Optional OneBank Top Connector A Mechanical Drawings Figure 6-9 Optional OneBank 0.600” (15.24mm) Connector ASP-129637-13 or equivalent Mechanical Drawings PCIe/104 and PCI/104-Express Specification Revision 3.
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Figure 6-10 Optional OneBank 0.866” (22mm) Connector ASP-142781-07 or equivalent Mechanical Drawings PCIe/104 and PCI/104-Express Specification Revision 3.
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6.1.6 Standard ASP-129646-03 or equivalent (Bottom Connector) Mechanical Drawings Figure 6-11: Standard ASP-129646-03 or equivalent Mechanical Drawings PCIe/104 and PCI/104-Express Specification Revision 3.
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6.1.7 Optional ASP-129646-22 (OneBank Bottom Connector) Mechanical Drawings Figure 6-12 Optional OneBank ASP-129646-22 or equivalent Mechanical Drawings 6.2. Connector B Connector B is the standard PCI bus that is used on PC/104-Plus and PCI-104 modules. See the PC/104-Plus or PCI-104 Specification for mechanical specification details of the connector. PCIe/104 and PCI/104-Express Specification Revision 3.
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6.3. Board Layout & Dimensions 6.3.1 PCIe/104 Layout & Dimensions The outer mechanical dimensions for this module are identical to PCI/104-Express Specification with the exception of the removal of the PCI connector and some modifications to the I/O connector area. Dimensions are in inches / (millimeters) Top View Side View Bottom View Figure 6-13 PCIe/104 Module Dimensions PCIe/104 and PCI/104-Express Specification Revision 3.
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Dimensions are in inches / (millimeters) Top View Side View Bottom View Figure 6-14 PCIe/104 OneBank Module Dimensions PCIe/104 and PCI/104-Express Specification Revision 3.
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6.3.2 PCI/104-Express Layout & Dimensions The outer mechanical dimensions for this module are identical to PC/104-Plus Specification with the exception of the added connector (J3), modifications to the I/O connector area, and changes to the component height restrictions. The component height on the top has been reduced from 0.435" to 0.345" and the bottom has been increased from 0.100" to 0.190".
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Dimensions are in inches / (millimeters) Top View Side View Bottom View Figure 6-16 PCI/104-Express OneBank Module Dimensions PCIe/104 and PCI/104-Express Specification Revision 3.
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6.3.3 Connector A Placement Details Since the QFS (ASP-129646-03) connector is larger than the QMS (ASP-129637-03), the QFS was used to determine the placement of both the QFS and the QMS. The maximum width of the QFS is determined by the recommend solder pad size and placement which is larger than the outer plastic dimensions of the QFS connector.
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6.4. Standoff Standoffs are used to ensure stacked boards retain their connectivity. The standoffs are preferably made from stainlesssteel to provide for maximum strength and height tolerance. Pads must be provided for the standoffs, with the same plating as the pads for the PCI Express connectors. All critical dimensions are listed. It is up to the user to define the thread type. The height of the standoff shall be 0.600 inches ±0.005 inches (15.24mm ±0.127mm).
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APPENDIX A: PC/104 BRIDGE CARD While advancing the PC/104 family of specifications, maintaining the stackable PCI bus was chosen over the stackable ISA bus for two reasons. First, many current and most future modern chipsets support both PCI and PCI Express. None support ISA. Second, backward compatibility to PC/104, PC/104-Plus, and PCI-104 is mechanically easier to achieve if the stackable PCI bus is retained over the stackable ISA bus.
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A.1 Bridge Module Configurations The PCI-to-ISA Bridge module has three possible configurations: Basic, Stack-UP only, and Stack-DOWN Only. Because of the heights of the Q2 (PCI/104-Express and PCIe/104) connectors and the ISA Bus (PC/104-Plus) connector and because they reside in the same general location, interference can occur if a PCI-to-ISA Bridge module is placed next to PCI/104-Express or PCIe/104 module.. In this case a Stack-UP Only or a Stack-DOWN Only version must be used.
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PCI Memory Chipset P rocessor Chip PCI/104-Express CPU Module PCI PCI PCIe 0.600 inches 15.2 4 mm) PCIe Device PCI/104-Express Peripheral Module PCI PCIe 0.600 inches (15.24 mm) PCI Device PCI-104 Peripheral Module PCI PCI ISA 0.600 inches (15.24 mm) ISA 0.600 inches (15.24 mm) ISA 0.600 inches (15.
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ISA ISA Device PC/104 Peripheral Module ISA 0.600 inches (15.24 mm) ISA 0.600 inches (15.24 mm) ISA Device PC/104 Peripheral Module PCI PCI-to-ISA Bridge Device PC/104-Plus Bridge Module PCI PCI 0.600 inches (15.24 mm) PCIe Device PCI/104-Express Peripheral Module PCIe PCI 0.600 inches (15.24 mm) Memory Chipset PCI/104-Express CPU Module Processor Chip PCI PCI PCIe Figure 6-23: Combined Stack-UP Configuration Example PCIe/104 and PCI/104-Express Specification Revision 3.
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APPENDIX B: EPIC FORM FACTOR – PCI/104-Express Placement 6.096 (159.92) 6.296 (154.84) (147.22) 5.796 (139.60) 5.496 (137.06) 5.394 (73.56) 2.896 (67.21) 2.646 (65.94) 2.596 (57.05) 2.246 (44.35) 1.746 (40.64) 1.600 (3.18) 0.125 (0.00) 0.000 (-5.08) -0.200 4.328 (109.93) (109.93) 4.328 I/O Zone 3 (104.86) 4.128 (101.68) 4.003 4.128 (104.85) 4.003 (101.68) (97.23) 3.828 0.250 (6.35) DIA. PAD 0.125 (3.18) DIA. HOLE 8 PLCS PC/104 PCI Connector I/O Zone 2 Stackable PCIe Connector (22.
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APPENDIX C: EBX FORM FACTOR – PCI/104-Express Placement 8.300 (210.82) 7.800 (198.12) 7.600 (193.04) 7.000 (177.80) 6.000 (152.40) 5.700 (144.78) 3.100 (78.74) 2.800 (71.12) 1.000 (25.40) 0.125 (3.18) 0.000 (0.00) -0.200 (-5.08) -0.200 (-5.08) -0.200 (-5.08) 0.000 (0.00) SIMM/DIMM Memory Zone 0.000 (0.00) 0.150 (3.81) A Power Connector Zone 0.650 (16.51) Tall CPU Region (option) General Purpose I/O Zone D 1.875 (47.63) 2.000 (50.80) B E 1.675 (42.55) 1.675 (42.55) 2.000 (50.