9-1423; Rev 0; 3/99 KIT ATION EVALU E L B A AVAIL +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC The MAX1402 low-power, multichannel, serial-output analog-to-digital converter (ADC) features matched 200µA current sources for sensor excitation. This ADC uses a sigma-delta modulator with a digital decimation filter to achieve 16-bit accuracy. The digital filter’s userselectable decimation factor allows the conversion resolution to be reduced in exchange for a higher output data rate.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC ABSOLUTE MAXIMUM RATINGS Maximum Current Input into Any Pin ..................................50mA Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derate 9.52mW/°C above +70°C) ........524mW Operating Temperature Ranges MAX1402CAI .....................................................0°C to +70°C MAX1402EAI...................................................-40°C to +85°C Storage Temperature Range ............................
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC (V+ = +5V ±5%, VDD = +2.7V to +5.25V, VREFIN+ = +2.50V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OFFSET DAC Offset DAC Range (Note 6) Offset DAC Resolution Offset DAC Full-Scale Error Unipolar mode -116.7 116.7 Bipolar mode -58.35 58.35 Unipolar mode 16.7 Bipolar mode 8.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC ELECTRICAL CHARACTERISTICS (continued) (V+ = +5V ±5%, VDD = +2.7V to +5.25V, VREFIN+ = +2.50V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL AIN and REFIN Input Sampling Frequency fS REFIN+ - REFIN- Voltage (Note 13) CONDITIONS MIN TYP MAX (Table 15) ±5% for specified performance; functional with lower VREF UNITS Hz 2.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC (V+ = +5V ±5%, VDD = +2.7V to +5.25V, VREFIN+ = +2.50V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.75 5.25 V 2.7 5.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC ELECTRICAL CHARACTERISTICS (continued) (V+ = +5V ±5%, VDD = +2.7V to +5.25V, VREFIN+ = +2.50V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER 5V Digital Supply Current SYMBOL IDD CONDITIONS MIN TYP 4X mode, MF1 = 1, MF0 = 0 1.024MHz 0.17 2.4576MHz 0.36 8X mode, MF1 = 1, MF0 = 1 1.024MHz 0.24 2.4576MHz 0.53 MAX 0.6 UNITS mA 0.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC TIMING CHARACTERISTICS (V+ = +5V ±5%, VDD = +2.7V to +5.25V, AGND = DGND, fCLKIN = 2.4576MHz; input logic 0 = 0V; logic 1 = VDD, TA = TMIN to TMAX, unless otherwise noted.) (Notes 19, 20, 21) PARAMETER Master Clock Frequency SYMBOL CONDITIONS MIN TYP MAX Crystal oscillator or clock exterX2CLK = 0 nally supplied for specified perforX2CLK = 1 mance (Notes 22, 23) 0.4 2.5 fCLKIN 0.8 5.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC TIMING CHARACTERISTICS (continued) (V+ = +5V ±5%, VDD = +2.7V to +5.25V, AGND = DGND, fCLKIN = 2.4576MHz; input logic 0 = 0V; logic 1 = VDD, TA = TMIN to TMAX, unless otherwise noted.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC INTEGRAL NONLINEARITY AT 480sps, GAIN = 1 (262, 144 pts) 10 5 DNL (ppm) INL (ppm) 100 0 0 1 2 3 4 0 -5 -5 -10 -10 -15 0 5 -15 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 COMPLIANCE VOLTAGE (V) DIFFERENTIAL INPUT VOLTAGE (V) CODE (x105) VDD SUPPLY CURRENT vs. TEMPERATURE (20sps OUTPUT DATA RATE UNBUFFERED) VDD SUPPLY CURRENT vs.
Typical Operating Characteristics (continued) (V+ = +5V, VDD = +5V, VREFIN+ = +2.50V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = +25°C, unless otherwise noted.) VDD SUPPLY CURRENT (µA) 400 350 VDD = +5.25V 300 250 200 150 VDD = +3.6V 100 600 VDD SUPPLY CURRENT (µA) MAX1402 toc05 450 MAX1402 toc06 VDD SUPPLY CURRENT vs. TEMPERATURE (480sps OUTPUT DATA RATE UNBUFFERED) VDD SUPPLY CURRENT vs. TEMPERATURE (240sps OUTPUT DATA RATE UNBUFFERED) 500 VDD = +5.25V 400 300 200 VDD = +3.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC PIN NAME FUNCTION 1 CLKIN Clock Input. A crystal can be connected across CLKIN and CLKOUT. Alternatively, drive CLKIN with a CMOS-compatible clock at a nominal frequency of 2.4576MHz or 1.024MHz, and leave CLKOUT unconnected. Frequencies of 4.9152MHz and 2.048MHz may be used if the X2CLK control bit is set to 1. 2 CLKOUT Clock Output. When deriving the master clock from a crystal, connect the crystal between CLKIN and CLKOUT.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1402 Pin Description (continued) PIN FUNCTION CALGAIN- Negative Gain Calibration Input. Used for system-gain calibration. It forms the negative input of a fully differential input pair with CALGAIN+. Normally these inputs are connected to reference voltages in the system.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Two chopper-stabilized buffers are available to isolate the selected inputs from the capacitive loading of the PGA and modulator. Three independent DACs provide compensation for the DC component of the input signal on each of the differential input channels.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC The MAX1402 can be configured to sequentially scan all signal inputs and to transmit the results through the serial interface with minimum communications overhead. The output word contains a result identification tag to indicate the source of each conversion result. The MAX1402 features a mode where the raw modulator data output is accessible.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Data-Ready Signal (DRDY bit true or INT = low) The data-ready signal indicates that new data may be read from the 24-bit data register. After the end of a successful data register read, the data-ready signal becomes false. If a new measurement completes before the data is read, the data-ready signal becomes false. The data-ready signal becomes true again when new data is available in the data register.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC are held in reset, inhibiting normal self-timed operation. This bit may be used to convert on command to minimize the settling time to valid output data, or to synchronize operation of a number of MAX1402s. FSYNC does not reset the serial interface or the 0/DRDY flag. To clear the 0/DRDY flag while FSYNC is active, simply read the data register. Global Setup Register 1 A1, A0: (Default = 0, 0) Channel-Selection Control Bits.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC BOUT: (Default = 0) Burn-out Current Bit. Setting BOUT = 1 connects 100nA current sources to the selected analog input channel. This mode is used to check that a transducer has not burned out or opened circuit. The burn-out current source must be turned off (BOUT = 0) before measurement to ensure best linearity. IOUT: (Default = 0) The IOUT bit controls the Transducer Excitation Currents.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 4.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC mapped to the correct output range. Note U/B must be set before a conversion is performed; it will not affect any data already held in the output register. Selecting bipolar mode does not imply that any input may be taken below AGND. It simply changes the gain and offset of the part. All inputs must remain within their specified operating voltage range.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 8. Transfer-Function Register Mapping—Normal Mode (M1 = 0, M0 = 0) SCAN DIFF A1 A0 CHANNEL TRANSFER FUNCTION REG.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1402 Table 9. Transfer-Function Register Mapping—Offset-Cal Mode (M1 = 0, M0 = 1) SCAN DIFF A1 A0 CHANNEL TRANSFER FUNCTION REG.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 10. Transfer-Function Register Mapping—Gain-Cal Mode (M1 = 1, M0 = 0) TRANSFER FUNCTION REG.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC CID2–0: Channel ID tag (Table 11). Switching Network A switching network provides selection between three fully differential input channels or five pseudo-differential channels, using AIN6 as a shared common. The switching network provides two additional fully differential input channels intended for system calibration, which may be used as extra fully differential signal channels.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC TC matching. Optimized for transducer excitation, the current sources possess tight temperature tracking allowing accurate compensation of errors due to IR drops in long transducer cable runs. They may be enabled or disabled using a single register control bit (IOUT).
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC EXTERNAL RESISTANCE REXT (kΩ) PGA GAIN CEXT = 0pF CEXT = 50pF CEXT = 100pF CEXT = 500pF CEXT = 1000pF CEXT = 5000pF 1 11.1 4.9 3.2 0.95 0.54 0.14 2 11.1 4.9 3.2 0.95 0.54 0.14 4 8.3 4.2 2.9 0.89 0.50 0.13 8, 16, 32, 64, 128 5.5 3.3 2.4 0.81 0.46 0.12 Table 13d.
Table 14. REXT, CEXT Values for Less than 16-Bit Gain Error in Buffered (BUFF = 1) Mode—All Modulator Sampling Frequencies (MF1, MF0 = XX); X2CLK = 0; CLKIN = 2.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MCLK FREQ. X2CLK = 0 DEFAULT fCLKIN (MHz) MCLK FREQ. X2CLK = 1 fCLKIN (MHz) CLK MF1 MF0 AIN/REFIN SAMPLING FREQ. fS (kHz) MOD. FREQ. fM (kHz) AVAILABLE OUTPUT DATA RATES AT 16-BIT ACCURACY (sps) 1.024 2.048 0 0 0 1.024 2.048 0 0 1 16 8 20, 25 32 16 40, 50 1.024 2.048 0 1 1.024 2.048 0 1 0 64 32 80, 100 1 128 64 160, 200 2.4576 4.9152 1 0 0 38.4 19.2 50, 60 2.4576 4.9152 2.4576 4.
Table 16b. MAX1402 Noise vs. Gain and Output Data Rate—Buffered Mode, VREF = 2.5V, fCLKIN = 2.4576MHz OUTPUT DATA RATE (sps) -3dB FREQ. (Hz) 50 13.1 TYPICAL OUTPUT NOISE IN µVRMS BIT STATUS PROGRAMMABLE GAIN x1 6.05 x2 4.13 x4 2.35 x8 1.50 x16 1.40 x32 1.32 x64 1.37 x128 1.39 MF1:MF0 = 0 FS1:FS0 = 0 60 15.7 7.11 4.24 2.54 1.64 1.49 1.53 1.49 1.48 FS1:FS0 = 1 300 78.6 142.02 71.62 35.65 18.32 9.35 5.60 4.10 3.52 FS1:FS0 = 2 600 157.2 823.33 405.95 195.95 102.14 50.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC with a 50% duty cycle. To activate this prescaler, set the X2CLK bit in the control registers. Note that using CLKIN frequencies above 2.5MHz in combination with the X2CLK mode will result in a small increase in digital supply current. Offset-Correction DAC The on-chip digital filter processes the 1-bit data stream from the modulator using a SINC3 or SINC1 filter.
when valid data is available, a minimum of three dataword periods later. The digital filter can be bypassed by setting the MDOUT bit in the global setup register. When MDOUT = 1, the raw output of the modulator is directly available at DOUT. Filter Characteristics The MAX1402 digital filter implements both a SINC1 (sinx/x) and SINC3 (sinx/x)3 lowpass filter function.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Depending on the application, it may be necessary to provide filtering prior to the MAX1402 to eliminate unwanted frequencies the digital filter does not reject. It may also be necessary in some applications to provide additional filtering to ensure that differential noise signals outside the frequency band of interest do not saturate the analog modulator.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC /* Assumptions: ** The MAX140X's CS pin is tied to ground ** The MAX140X's INT pin drives a falling-edge-triggered interrupt ** MAX140X's DIN is driven by MOSI, DOUT drives MISO, and SCLK drives SCLK */ /* Low-level function to write 8 bits using 68HC11 SPI */ void WriteByte (BYTE x) { /* System-dependent: write to SPI hardware and wait until it is finished */ HC11_SPDR = x; while (HC11_SPSR & HC11_SPSR_SPIF) { /* idle loop */ } }
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1402 VDD RESET 8051 P3.0 DOUT MAX1402 DIN P3.1 SCLK CS Figure 14.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC ANALOG SUPPLY V+ REFIN+ VDD V+ RREF CLOCK GEN DIVIDER MAX1402 CLKIN CLKOUT REFINACTIVE GAUGE BUFFER BUFFER R SWITCHING NETWORK AIN1 AIN2 DUMMY GAUGE PGA ADDITIONAL ANALOG AND CALIBRATION CHANNELS R MODULATOR DIGITAL FILTER BUFFER BUFFER DAC OUT1 INTERFACE AND CONTROL AGND OUT2 AGND SCLK DIN DOUT INT CS RESET DS1 DS0 DGND Figure 16.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Power Supplies No specific power sequence is required for the MAX1402; either the V+ or the VDD supply can come up first. While the latchup performance of the MAX1402 is good, it is important that power be applied to the MAX1402 before the analog input signals (AIN_) or the CLKIN inputs, to avoid latchup. If this is not possible, then the current flow into any of these pins should be limited to 50mA.
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC V+ VDD 200µA REFIN+ REFIN- OUT1 12.5k AIN1 MODULATOR RL1 RTD PGA AIN2 A = 1 TO 128 OUT2 RL2 200µA MAX1402 AGND RL3 DGND Figure 19. 3-Wire RTD Application perature drift of the RTD current source and compensated for by the variation in the reference voltage. A common resistance value for the RTD is 100Ω generating a 20mV signal directly handled at the analog input of the MAX1402.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1402 ISO +5V +5V V+ VDD +VDD 200µA 2k OUT2 VCC MAX1402 6N136 DIN REFIN+ MODULATOR RREF REFIN- 470Ω MOSI 200µA OUT1 2k VCC 6N136 MAX1402 SCLK AIN1 470Ω SCK RTD VCC PGA AIN2 2k 470Ω A = 1 TO 128 6N136 MISO AGND DGND DOUT VCC Figure 20. 4-Wire RTD Application 2k board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is important when using high-resolution ADCs.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC SSOP.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC ______________________________________________________________________________________ MAX1402 NOTES 39
MAX1402 +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
