Specifications

END CPLD HIERARCHY BLOCK
MEM_SCK
10K
97_IO
10K
10K
2.7V
.1UF
MEM_CS MEM_SO
MEM_SI
I27
I18
L_TDI L_TDO L_TCK L_TMS
CPU_RESET
L_TMS L_TDO L_TDI L_TCK
I12
I3 I7
10K
MEM_SCK
10UF
10UF
10UF
.1UF
.1UF
I29
V1_2
V1_2
TPB02
1
RB03
RB05
TPB01
1
U01
94
91 90 89
97
128
117
98
109
72
80
63
52
28
37
144
15
96
95
11
12
93
14 16 18 17
13
92 99 54
126
136
143
110
125
108
73
84
55
71
38
44
24
36
1
19 10
CB02
RB02
RB01
JB01
1
2
3
4
5 6
7
8
9
10
CB01
CB08
CB09
CB10
CB11
UB02
1
4
7
6 5 2
8
3
UB01
2
5
1
6 4
3
DS33M33DK01A0
24/26(TOTAL)
STEVE SCULLY
2/2(BLOCK)
10/03/2007
BLOCK NAME: overheadcpld_dn_. PARENT BLOCK: \_rc_top_dn_\
OVERHEAD. P.2,10,23-24
CR-50 : @\_rc_lib\.\_rc_top_dn_\(sch_1):page12_i24@\_rc_lib\.\overheadcpld_dn_\(sch_1):Page2
11B5^
23B3
24B1
23B4
23C4
23C4
24C4 24C4 24C4 24C4
24D6 24D6 24D6 24D6
24A5
24C1
PAGE: DATE:
TITLE:
ENGINEER:
A A B B C C D
D
1
1
2
2
3
3
4
45
56
6
7
7
8 8
V3_3
MAX1963
SHDN* GND
RST*
OUT
IC
IN
V3_3
AT25160A_U
SI
GND WP*
HOLD*
VCC
SO SCK CS*
V3_3
CONN_10P
7
1
5 GND
3
TCK TMS TDI
VCC
TDO
V3_3 V3_3
CONTROL
LFEC_T144_U
ALL LOW FOR SPI3 MODE
NEEDS 10K,1% RESISTOR
PLACE CLOSE TO PIN
VCCIO4A
VCCIO3B
XRES
VCCAUX2 VCCAUX1
VCCJ VCC3
TDI TDO
VCCIO3A
VCCIO4B
VCCIO5A
VCCIO2
VCCIO1B
VCCIO1A
VCCIO0B
INIT*
PROGRAM*
VCCIO0A
CCLK
CFG1 CFG2 CFG0 TMS
VCC2 VCC1
VCCIO5B
VCCIO6A
TCK
DONE
GND10
GND9
GND8
GND7/GND0
GND6B/GND5
GND3B
GND3A/GND4
GND2/GND1
GND1
GND0
NC1
NC2
GND4
GND6A
GND5
VCCIO7
VCCIO6B
IN