Specifications

_________________________________________________________________________________________________ DS33M33DK
Rev: 102108 13 of 48
Register Name: GPIOAwr
Register Description: GPIO A Output Enable + Write Value
Register Offset: 0x0003
Bit # 7 6 5 4 3 2 1 0
Name
— —
GPIOa3
Output En
GPIOa3
Value
GPIOa2
Output En
GPIOa2
Value
GPIOa1
Output En
GPIOa1
Value
Default 0 0 0 0 0 0 0 0
Bits 5 and 4: DS33M33 GPIOA_3 Three-State and Level
0x = FPGA three-states GPIOA_3 pin
00 = FPGA drives GPIOA_3 pin with 0.0V
01 = FPGA drives GPIOA_3 pin with 3.3V
Bits 3 and 2: DS33M33 GPIOA_2 Three-State and Level
0x = FPGA three-states GPIOA_2 pin
00 = FPGA drives GPIOA_2 pin with 0.0V
01 = FPGA drives GPIOA_2 pin with 3.3V
Bits 1 and 0: DS33M33 GPIOA_1 Three-State and Level
0x = FPGA three-states GPIOA_1 pin
00 = FPGA drives GPIOA_1 pin with 0.0V
01 = FPGA drives GPIOA_1 pin with 3.3V
Register Name: GPIOBwr
Register Description: GPIO B Output Enable + Write Value
Register Offset: 0x0004
Bit # 7 6 5 4 3 2 1 0
Name
— —
GPIOb3
Output En
GPIOb3
Value
GPIOb2
Output En
GPIOb2
Value
GPIOb1
Output En
GPIOb1
Value
Default 0 0 0 0 0 0 0 0
Bits 5 and 4: DS33M33 GPIOB_3 Three-State and Level control
0x = FPGA three-states GPIOB_3 pin
00 = FPGA drives GPIOB_3 pin with 0.0V
01 = FPGA drives GPIOB_3 pin with 3.3V
Bits 3 and 2: DS33M33 GPIOB_2 Three-State and Level control
0x = FPGA three-states GPIOB_2 pin
00 = FPGA drives GPIOB_2 pin with 0.0V
01 = FPGA drives GPIOB_2 pin with 3.3V
Bits 1 and 0: DS33M33 GPIOB_1 Three-State and Level control
0x = FPGA three-states GPIOB_1 pin
00 = FPGA drives GPIOB_1 pin with 0.0V
01 = FPGA drives GPIOB_1 pin with 3.3V