Datasheet
Table Of Contents
- FEATURES
- DETAILED DESCRIPTION
- ORDERING INFORMATION
- Figure 1. Block Diagram
- PIN DESCRIPTION
- 80C32 COMPATIBILITY
- Figure 2. Comparative Timing of the DS80C320/DS80C323 and 80C32
- HIGH-SPEED OPERATION
- INSTRUCTION SET SUMMARY
- Table 1. Instruction Set Summary
- SPEED ADVANTAGE SUMMARY
- MEMORY ACCESS
- Figure 3. Typical Memory Connection
- STRETCH MEMORY CYCLE
- Table 2. Data Memory Cycle Stretch Values
- DUAL DATA POINTER
- 64-Byte Block Move without Dual Data Pointer
- 64-Byte Block Move with Dual Data Pointer
- PERIPHERAL OVERVIEW
- SERIAL PORTS
- TIMER-RATE CONTROL
- POWER-FAIL RESET
- POWER-FAIL INTERRUPT
- WATCHDOG TIMER
- Table 3. Watchdog Timeout Values
- INTERRUPTS
- Table 4. Interrupt Priority
- POWER MANAGEMENT
- IDLE MODE ENHANCEMENTS
- STOP MODE ENHANCEMENTS
- Figure 4. Ring Oscillator Startup
- TIMED ACCESS PROTECTION
- SPECIAL-FUNCTION REGISTERS
- Table 5. Special-Function Register Locations
- ELECTRICAL SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- DC ELECTRICAL CHARACTERISTICS—DS80C320
- NOTES FOR DS80C320 DC ELECTRICAL CHARACTERISTICS
- TYPICAL ICC vs. FREQUENCY
- AC CHARACTERISTICS—DS80C320
- NOTES FOR DS80C320 AC ELECTRICAL CHARACTERISTICS
- MOVX CHARACTERISTICS—DS80C320
- DC ELECTRICAL CHARACTERISTICS—DS80C323
- NOTES FOR DS80C323 DC ELECTRICAL CHARACTERISTICS
- NOTES FOR DS80C323 DC ELECTRICAL CHARACTERISTICS (continued)
- AC ELECTRICAL CHARACTERISTICS—DS80C323
- NOTES FOR DS80C323 AC ELECTRICAL CHARACTERISTICS
- MOVX CHARACTERISTICS—DS80C323
- EXTERNAL CLOCK CHARACTERISTICS
- SERIAL PORT MODE 0 TIMING CHARACTERISTICS
- EXPLANATION OF AC SYMBOLS
- POWER-CYCLE TIMING CHARACTERISTICS
- NOTES FOR POWER CYCLE TIMING CHARACTERISTICS
- PROGRAM MEMORY READ CYCLE
- DATA MEMORY READ CYCLE
- DATA MEMORY WRITE CYCLE
- DATA MEMORY WRITE WITH STRETCH = 1
- DATA MEMORY WRITE WITH STRETCH = 2
- EXTERNAL CLOCK DRIVE
- SERIAL PORT MODE 0 TIMING
- POWER-CYCLE TIMING
- DATA SHEET REVISION SUMMARY
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
19 of 38
Figure 4. Ring Oscillator Startup
TIMED ACCESS PROTECTION
Selected SFR bits are critical to operation, making it desirable to protect against an accidental write
operation. The Timed Access procedure prevents an errant CPU from accidentally altering a bit that
would cause difficulty. The Timed Access procedure requires that the write of a protected bit be preceded
by the following instructions:
MOV 0C7h, #0AAh
MOV 0C7h, #55h
By writing an AAh followed by a 55h to the Timed Access register (location C7h), the hardware opens a
three-cycle window that allows software to modify one of the protected bits. If the instruction that seeks
to modify the protected bit is not immediately proceeded by these instructions, the write will not take
effect. The protected bits are:
EXIF.0 BGS Bandgap Select
WDCON.6 POR Power-on Reset flag
WDCON.1 EWT Enable Watchdog
WDCON.0 RWT Reset Watchdog
WDCON.3 WDIF Watchdog Interrupt Flag
DIAGRAM ASSUMES THAT THE OPERATION FOLLOWING STOP REQUIRES LESS THAN 18ms COMPLETE.