Datasheet
Table Of Contents
- FEATURES
- DETAILED DESCRIPTION
- ORDERING INFORMATION
- Figure 1. Block Diagram
- PIN DESCRIPTION
- 80C32 COMPATIBILITY
- Figure 2. Comparative Timing of the DS80C320/DS80C323 and 80C32
- HIGH-SPEED OPERATION
- INSTRUCTION SET SUMMARY
- Table 1. Instruction Set Summary
- SPEED ADVANTAGE SUMMARY
- MEMORY ACCESS
- Figure 3. Typical Memory Connection
- STRETCH MEMORY CYCLE
- Table 2. Data Memory Cycle Stretch Values
- DUAL DATA POINTER
- 64-Byte Block Move without Dual Data Pointer
- 64-Byte Block Move with Dual Data Pointer
- PERIPHERAL OVERVIEW
- SERIAL PORTS
- TIMER-RATE CONTROL
- POWER-FAIL RESET
- POWER-FAIL INTERRUPT
- WATCHDOG TIMER
- Table 3. Watchdog Timeout Values
- INTERRUPTS
- Table 4. Interrupt Priority
- POWER MANAGEMENT
- IDLE MODE ENHANCEMENTS
- STOP MODE ENHANCEMENTS
- Figure 4. Ring Oscillator Startup
- TIMED ACCESS PROTECTION
- SPECIAL-FUNCTION REGISTERS
- Table 5. Special-Function Register Locations
- ELECTRICAL SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- DC ELECTRICAL CHARACTERISTICS—DS80C320
- NOTES FOR DS80C320 DC ELECTRICAL CHARACTERISTICS
- TYPICAL ICC vs. FREQUENCY
- AC CHARACTERISTICS—DS80C320
- NOTES FOR DS80C320 AC ELECTRICAL CHARACTERISTICS
- MOVX CHARACTERISTICS—DS80C320
- DC ELECTRICAL CHARACTERISTICS—DS80C323
- NOTES FOR DS80C323 DC ELECTRICAL CHARACTERISTICS
- NOTES FOR DS80C323 DC ELECTRICAL CHARACTERISTICS (continued)
- AC ELECTRICAL CHARACTERISTICS—DS80C323
- NOTES FOR DS80C323 AC ELECTRICAL CHARACTERISTICS
- MOVX CHARACTERISTICS—DS80C323
- EXTERNAL CLOCK CHARACTERISTICS
- SERIAL PORT MODE 0 TIMING CHARACTERISTICS
- EXPLANATION OF AC SYMBOLS
- POWER-CYCLE TIMING CHARACTERISTICS
- NOTES FOR POWER CYCLE TIMING CHARACTERISTICS
- PROGRAM MEMORY READ CYCLE
- DATA MEMORY READ CYCLE
- DATA MEMORY WRITE CYCLE
- DATA MEMORY WRITE WITH STRETCH = 1
- DATA MEMORY WRITE WITH STRETCH = 2
- EXTERNAL CLOCK DRIVE
- SERIAL PORT MODE 0 TIMING
- POWER-CYCLE TIMING
- DATA SHEET REVISION SUMMARY
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
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POWER MANAGEMENT
The DS80C320/DS80C323 provide the standard Idle and power-down (Stop) modes that are available on
the standard 80C32. However, the device has enhancements that make these modes more useful, and
allow more power saving.
The Idle mode is invoked by setting the LSB of the Power Control register (PCON to 87h). Idle will leave
internal clocks, serial port and timer running. No memory access will be performed so power is
dramatically reduced. Since clocks are running, the Idle power consumption is related to crystal
frequency. It should be approximately one-half the operational power. The CPU can exit the Idle state
with any interrupt or a reset.
The power-down or Stop mode is invoked by setting the PCON.1 bit. Stop mode is a lower power state
than Idle since it turns off all internal clocking. The I
CC
of a standard Stop mode is approximately 1 µA
but is specified in the Electrical Specifications section. The CPU will exit Stop mode from an external
interrupt or a reset condition.
Note that internally generated interrupts (timer, serial port, watchdog) are not useful in Idle or Stop since
they require clocking activity.
IDLE MODE ENHANCEMENTS
A simple enhancement to Idle mode makes it substantially more useful. The innovation involves not the
Idle mode itself, but the watchdog timer. As mentioned above, the Watchdog Timer provides an optional
interrupt capability. This interrupt can provide a periodic interval timer to bring the
DS80C320/DS80C323 out of Idle mode. This can be useful even if the Watchdog is not normally used.
By enabling the Watchdog Timer and its interrupt prior to invoking Idle, a user can periodically come out
of Idle perform an operation, then return to Idle until the next operation. This will lower the overall power
consumption. When using the Watchdog Interrupt to cancel the Idle state, make sure to restart the
Watchdog Timer or it will cause a reset.
STOP MODE ENHANCEMENTS
The DS80C320/DS80C323 provide two enhancements to the Stop mode. As documented above, the
device provides a bandgap reference to determine Power-fail Interrupt and Reset thresholds. The default
state is that the bandgap reference is off when Stop mode is invoked. This allows the extremely low
power state mentioned above. A user can optionally choose to have the bandgap enabled during Stop
mode. This means that PFI and power-fail reset will be activated and are valid means for leaving Stop
mode.
In Stop mode with the bandgap on, I
CC
will be approximately 50A compared with 1A with the bandgap
off. If a user does not require a Power-fail Reset or Interrupt while in Stop mode, the bandgap can remain
turned off. Note that only the most power sensitive applications should turn off the bandgap, as this
results in an uncontrolled power-down condition.
The control of the bandgap reference is located in the Extended Interrupt Flag register (EXIF to 91h).
Setting BGS (EXIF.0) to a 1 will leave the bandgap reference enabled during Stop mode. The default or
reset condition is with the bit at a logic 0. This results in the bandgap being turned off during Stop mode.
Note that this bit has no control of the reference during full power or Idle modes. Be aware that the
DS80C320 and DS80C323 require that the reset watchdog timer bit (RWT;WDCON.0) be set