Datasheet
Table Of Contents
- FEATURES
- DETAILED DESCRIPTION
- ORDERING INFORMATION
- Figure 1. Block Diagram
- PIN DESCRIPTION
- 80C32 COMPATIBILITY
- Figure 2. Comparative Timing of the DS80C320/DS80C323 and 80C32
- HIGH-SPEED OPERATION
- INSTRUCTION SET SUMMARY
- Table 1. Instruction Set Summary
- SPEED ADVANTAGE SUMMARY
- MEMORY ACCESS
- Figure 3. Typical Memory Connection
- STRETCH MEMORY CYCLE
- Table 2. Data Memory Cycle Stretch Values
- DUAL DATA POINTER
- 64-Byte Block Move without Dual Data Pointer
- 64-Byte Block Move with Dual Data Pointer
- PERIPHERAL OVERVIEW
- SERIAL PORTS
- TIMER-RATE CONTROL
- POWER-FAIL RESET
- POWER-FAIL INTERRUPT
- WATCHDOG TIMER
- Table 3. Watchdog Timeout Values
- INTERRUPTS
- Table 4. Interrupt Priority
- POWER MANAGEMENT
- IDLE MODE ENHANCEMENTS
- STOP MODE ENHANCEMENTS
- Figure 4. Ring Oscillator Startup
- TIMED ACCESS PROTECTION
- SPECIAL-FUNCTION REGISTERS
- Table 5. Special-Function Register Locations
- ELECTRICAL SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- DC ELECTRICAL CHARACTERISTICS—DS80C320
- NOTES FOR DS80C320 DC ELECTRICAL CHARACTERISTICS
- TYPICAL ICC vs. FREQUENCY
- AC CHARACTERISTICS—DS80C320
- NOTES FOR DS80C320 AC ELECTRICAL CHARACTERISTICS
- MOVX CHARACTERISTICS—DS80C320
- DC ELECTRICAL CHARACTERISTICS—DS80C323
- NOTES FOR DS80C323 DC ELECTRICAL CHARACTERISTICS
- NOTES FOR DS80C323 DC ELECTRICAL CHARACTERISTICS (continued)
- AC ELECTRICAL CHARACTERISTICS—DS80C323
- NOTES FOR DS80C323 AC ELECTRICAL CHARACTERISTICS
- MOVX CHARACTERISTICS—DS80C323
- EXTERNAL CLOCK CHARACTERISTICS
- SERIAL PORT MODE 0 TIMING CHARACTERISTICS
- EXPLANATION OF AC SYMBOLS
- POWER-CYCLE TIMING CHARACTERISTICS
- NOTES FOR POWER CYCLE TIMING CHARACTERISTICS
- PROGRAM MEMORY READ CYCLE
- DATA MEMORY READ CYCLE
- DATA MEMORY WRITE CYCLE
- DATA MEMORY WRITE WITH STRETCH = 1
- DATA MEMORY WRITE WITH STRETCH = 2
- EXTERNAL CLOCK DRIVE
- SERIAL PORT MODE 0 TIMING
- POWER-CYCLE TIMING
- DATA SHEET REVISION SUMMARY
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
12 of 38
STRETCH MEMORY CYCLE
The DS80C320/DS80C323 allow the application software to adjust the speed of data memory access. The
microcontroller is capable of performing the MOVX in as little as two instruction cycles. However, this
value can be stretched as needed so that both fast memory and slow memory or peripherals can be
accessed with no glue logic. Even in high-speed systems, it may not be necessary or desirable to perform
data memory access at full speed. In addition, there are a variety of memory-mapped peripherals such as
LCD displays or UARTs that are not fast.
The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below.
This allows the user to select a stretch value between 0 and 7. A Stretch of 0 will result in a two-machine
cycle MOVX. A Stretch of 7 will result in a MOVX of nine machine cycles. Software can dynamically
change this value depending on the particular memory or peripheral.
On reset, the Stretch value will default to 1, resulting in a three-cycle MOVX. Therefore, RAM access
will not be performed at full speed. This is a convenience to existing designs that may not have fast RAM
in place. When maximum speed is desired, the software should select a Stretch value of 0. When using
very slow RAM or peripherals, a larger stretch value can be selected. Note that this affects data memory
only and the only way to slow program memory (ROM) access is to use a slower crystal.
Using a Stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all
related timing. This results in a wider read/write strobe allowing more time for memory/peripherals to
respond. The timing of the variable speed MOVX is shown in the Electrical Specifications section. Note
that full speed access is not the reset default case. Table 2 shows the resulting strobe widths for each
Stretch value. The memory stretch is implemented using the Clock Control special-function register at
SFR location 8Eh. The stretch value is selected using bits CKCON.2–0. In the table, these bits are
referred to as M2 through M0. The first stretch (default) allows the use of common 120ns or 150ns RAMs
without dramatically lengthening the memory access.
Table 2. Data Memory Cycle Stretch Values
CKCON.2–0
MD2 MD1 MD0
MEMORY
CYCLES
RD or WR STROBE
WIDTH IN CLOCKS
STROBE WIDTH
TIME AT 25MHz
(ns)
0 0 0 2 2 80
0 0 1 3 (default) 4 160
0 1 0 4 8 320
0 1 1 5 12 480
1 0 0 6 16 640
1 0 1 7 20 800
1 1 0 8 24 960
1 1 1 9 28 1120