Datasheet

Extremely Accurate I
2
C-Integrated
RTC/TCXO/Crystal
Figure 1. Timekeeping Registers
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.
A D D R ESS
BIT 7
MSB
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
BIT 0
LSB
FUNCTION RANGE
00h 0 10 Seconds Seconds Seconds 00–59
01h 0 10 Minutes Minutes Minutes 00–59
AM/PM
02h 0 12/24
20 Hour
10 Hour Hour Hours
1–12 + AM/PM
00–23
03h 0 0 0 0 0 Day Day 1–7
04h 0 0 10 Date Date Date 01–31
05h Century 0 0 10 Month Month
Month/
Century
01–12 +
Century
06h 10 Year Year Year 00–99
07h A1M1 10 Seconds Seconds Alarm 1 Seconds 00–59
08h A1M2 10 Minutes Minutes Alarm 1 Minutes 00–59
AM/PM
09h A1M3 12/24
20 Hour
10 Hour Hour Alarm 1 Hours
1–12 + AM/PM
00–23
Day Alarm 1 Day 1–7
0Ah A1M4 DY/DT 10 Date
Date Alarm 1 Date 1–31
0Bh A2M2 10 Minutes Minutes Alarm 2 Minutes 00–59
AM/PM
0Ch A2M3 12/24
20 Hour
10 Hour Hour Alarm 2 Hours
1–12 + AM/PM
00–23
Day Alarm 2 Day 1–7
0Dh A2M4 DY/DT 10 Date
Date Alarm 2 Date 1–31
0Eh EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE Control —
0Fh OSF 0 0 0 EN32kHz BSY A2F A1F Control/Status —
10h SIGN DATA DATA DATA DATA DATA DATA DATA Aging Offset —
11h SIGN DATA DATA DATA DATA DATA DATA DATA MSB of Temp —
12h DATA DATA 0 0 0 0 0 0 LSB of Temp —
Address Map
Figure 1 shows the address map for the DS3231 time-
keeping registers. During a multibyte access, when the
address pointer reaches the end of the register space
(12h), it wraps around to location 00h. On an I
2
C
START or address pointer incrementing to location 00h,
the current time is transferred to a second set of regis-
ters. The time information is read from these secondary
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the
main registers update during a read.
I
2
C Interface
The I
2
C interface is accessible whenever either V
CC
or
V
BAT
is at a valid level. If a microcontroller connected
to the DS3231 resets because of a loss of V
CC
or other
event, it is possible that the microcontroller and
DS3231 I
2
C communications could become unsyn-
chronized, e.g., the microcontroller resets while read-
ing data from the DS3231. When the microcontroller
resets, the DS3231 I
2
C interface may be placed into a
known state by toggling SCL until SDA is observed to
be at a high level. At that point the microcontroller
should pull SDA low while SCL is high, generating a
START condition.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Figure 1 illustrates
the RTC registers. The time and calendar data are set
or initialized by writing the appropriate register bytes.
The contents of the time and calendar registers are in
DS3231
Maxim Integrated
11