Datasheet

DS2413: 1-Wire Dual Channel Addressable Switch
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LEGACY VALUES DS2413 VALUES
PARAMETER STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED
MIN MAX MIN MAX MIN MAX MIN MAX
t
SLOT
(incl. t
REC
) 61µs (undef.) 7µs (undef.) 67µs (undef.) 10µs (undef.)
t
RSTL
480µs (undef.) 48µs 80µs 600µs 960µs 63µs 80µs
t
PDH
15µs 60µs 2µs 6µs 15µs 68µs 2µs 8.2µs
t
PDL
60µs 240µs 8µs 24µs 60µs 260µs 8µs 32µs
t
W0L
60µs 120µs 6µs 16µs 62µs 120µs 8µs 16µs
PIN DESCRIPTION
NAME TSOC PIN # TDFN PIN # FUNCTION
IO 2 2 1-Wire bus interface. Open-drain, requires external pullup resistor.
PIOA 6 4 Programmable I/O pin, open-drain with weak pulldown, power-on
default is off (PIOA = 1).
PIOB 4 6 Programmable I/O pin, open-drain with weak pulldown, power-on
default is off (PIOB = 1).
GND1 1 3 Ground reference 1
GND2 5 5 Ground reference 2; both GND pins must be connected in the
application.
NC 3 1 Not connected
GND — EP
Exposed Paddle (TDFN only). Solder evenly to the board’s ground
plane for proper operation. See Application Note 3273 for additional
information.
DESCRIPTION
The DS2413 combines two PIO pins and a fully featured 1-Wire interface in a single chip. PIO outputs are open-
drain, operate at up to 28V and provide an on resistance of 20 max. A robust communication protocol ensures
that PIO output changes occur error-free. Each DS2413 has a Registration Number that is 64 bits long. The
Registration Number guarantees unique identification and is used to address the device in a multidrop 1-Wire
network environment, where multiple devices reside on a common 1-Wire bus and operate independently of each
other. Device power is supplied parasitically from the 1-Wire bus. The DS2413’s applications of include accessory
identification and control, system monitoring, and general-purpose input/output.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major sections of the DS2413. The DS2413
has two main components: 64-bit Registration Number, and PIO Control. The hierarchical structure of the 1-Wire
protocol is shown in Figure 2. The bus master must first provide one of the seven ROM Function Commands, 1)
Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive-Skip ROM or 7) Overdrive-
Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device enters
Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these
ROM function commands is described in Figure 10. After a ROM function command is successfully executed, the
PIO functions become accessible and the master may provide one of the two PIO Function commands. The
protocol for these commands is described in Figure 6. All data is read and written least significant bit first.
Figure 1. Block Diagram
1-Wire
Interface
PIO
Control
64-Bit Registration
Number
PIOA
IO
Internal V
DD
PIOB