Datasheet

DS1307 64 x 8, Serial, I
2
C Real-Time Clock
4 of 14
TIMING DIAGRAM
Figure 1. Block Diagram
RAM
(56 X 8)
SERIAL BUS
INTERFACE
AND ADDRESS
REGISTER
CONTROL
LOGIC
1Hz
1Hz/4.096kHz/8.192kHz/32.768kHz
MUX/
BUFFER
USER BUFFER
(7 BYTES)
CLOCK,
CALENDAR,
AND CONTROL
REGISTERS
POWER
CONTROL
DS1307
X1
C
L
C
L
X2
SDA
SCL
SQW/OUT
V
CC
GND
V
BAT
Oscillator
and divider
N
START
SDA
STOP
SCL
t
SU:STO
t
HD:STA
t
SU:STA
REPEATED
START
t
HD:DAT
t
HIGH
t
F
t
LOW
t
R
t
HD:STA
t
BUF
SU:DA T